Semiconductor device and method of controlling the same

1. A semiconductor device comprising:

a memory cell array that includes non-volatile memory cells;

bit lines that are connected to sources and drains of transistors that form the memory cells;

word lines that are connected to gates of the transistors;

a plurality of divided regions that are contained in the memory cell array, each of the divided regions having memory cells connected to the same one of the word lines;

a plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines;

a plurality of cell blocks each having at least one bit contained in each of the divided regions, memory cells in each of the cell blocks being physically adjacent to one another; and

a connecting circuit that connects bit lines connected to neighboring memory cells to each other in the divided region;

wherein a first bit line connected to a first memory cell that is one of the memory cells in which data is to be written is precharged before the data is written in the first memory cell;

when the first bit line is precharged, the connecting circuit connects the first bit line to a second bit line connected to a second memory cell that is a memory cell neighboring the first memory cell in the divided region; and

before the data is written in the first memory cell, the connecting circuit disconnects the first bit line from the second bit line.

2. The semiconductor device of claim 1 , wherein, when the data is written in the first memory cell, the connecting circuit disconnects the first bit line from the second bit line.

3. The semiconductor device of claim 1 , wherein the connecting circuit comprising:

a selecting transistor that is connected to a first connecting line connected to the first bit line, and to a second connecting line connected to the second bit line.

4. The semiconductor device of claim 1 , wherein the plurality of divided regions that are contained in the memory cell array, each of the divided regions having memory cells connected to the same one of the word lines, data being read simultaneously from the memory cells of the same one of the divided regions.

5. The semiconductor device of claim 4 , wherein the plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines, data being written simultaneously in the memory cells of the same one of the sub divided regions.

6. The semiconductor device of claim 1 , wherein the plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines, data being written simultaneously in the memory cells of the same one of the sub divided regions.

7. The semiconductor device of claim 1 , wherein the semiconductor device is flash memory.

8. The semiconductor device of claim 1 , wherein the semiconductor device is NOR flash memory.

9. The semiconductor device of claim 1 , wherein the semiconductor device is NAND flash memory.

10. A method of controlling a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; bit lines that are connected to sources and drains of transistors that form the memory cells; word lines that are connected to gates of the transistors; a plurality of divided regions that are contained in the memory cell array, each of the divided regions having memory cells connected to the same one of the word lines; a plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines; and a plurality of cell blocks each having at least one bit contained in each of the divided regions, memory cells in each of the cell blocks being physically adjacent to one another,

the method comprising:

connecting a first bit line connected to a first memory cell that is a memory cell in which data is to be written, to a second bit line connected to a second memory cell that is a memory cell adjacent to the first memory cell in the divided region;

precharging the first bit line and the second bit line;

disconnecting the first bit line from the second bit line; and

after the disconnecting, writing the data in the first memory cell.

11. The method of claim 10 , wherein the plurality of divided regions that are contained in the memory cell array, each of the divided regions having memory cells connected to the same one of the word lines, data being read simultaneously from the memory cells of the same one of the divided regions.

12. The method of claim 11 , wherein the plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines, data being written simultaneously in the memory cells of the same one of the sub divided regions.

13. The method of claim 10 , wherein the plurality of sub divided regions that are contained in each of the divided regions, each of the sub divided regions having memory cells connected to the same one of the word lines, data being written simultaneously in the memory cells of the same one of the sub divided regions.

14. The method of claim 10 , wherein the non-volatile memory cells are virtual ground memory cells.

15. The method of claim 10 , wherein the semiconductor device is flash memory.

16. The method of claim 10 , wherein the semiconductor device is NOR flash memory.

17. The method of claim 10 , wherein the semiconductor device is NAND flash memory.