Semiconductor package and method of forming the same
Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.
1. A semiconductor package comprising:
a printed circuit board;
a first semiconductor chip on the printed circuit board; and
a chip package on the first semiconductor chip, the chip package including an interposer and a semiconductor chip group on the interposer, the interposer electrically connecting the semiconductor chip group to the first semiconductor chip,
wherein a first conductive terminal is disposed on an upper surface of the first semiconductor chip, a second conductive terminal is disposed on a lower surface of the interposer, and the first conductive terminal is also disposed on the second conductive terminal.
2. The semiconductor package of claim 1 , wherein the interposer includes a semiconductor substrate having through-hole vias.
3. The semiconductor package of claim 2 , wherein
the first conductive terminal includes first bump pads on an upper surface of the first semiconductor chip; and
the second conductive terminal includes first bumps on a lower surface of the interposer, the first bumps electrically connected to the through-hole vias and the first bump pads.
4. The semiconductor package of claim 1 , wherein the semiconductor chip group includes:
a second semiconductor chip having bumps connected to the through-hole vias, the second semiconductor chip being disposed on the interposer as a flip chip; and
a third semiconductor chip on the second semiconductor chip, the third semiconductor chip having bonding pads.
5. The semiconductor package of claim 4 , further comprising:
bonding wires electrically connecting the bonding pads and the through-hole vias.
6. The semiconductor package of claim 4 , further comprising:
an encapsulation layer covering the third semiconductor chip, the second semiconductor chip, and the interposer; and
a molding layer covering the encapsulation layer, the first semiconductor chip, and the printed circuit board.
7. The semiconductor package of claim 1 , wherein the first semiconductor chip includes a non-memory device, and the semiconductor chip group includes memory devices.
8. The semiconductor package of claim 1 , further comprising:
solder balls on a lower surface of the printed circuit board.
9. The semiconductor package of claim 1 , further comprising:
penetration interconnections within the semiconductor chip group, wherein the semiconductor chip group includes a plurality of semiconductor chips, the penetration interconnections extending through and electrically connecting the plurality of semiconductor chips.
10. The semiconductor package of claim 1 , wherein the chip package includes at least one semiconductor chip with a penetration interconnection extending completely through the at least one semiconductor chip.
11. The semiconductor package of claim 10 , wherein the at least one semiconductor chip with the penetration interconnection is not connected to a bonding wire.
12. The semiconductor package of claim 10 , wherein the at least one semiconductor chip with the penetration interconnection is not an uppermost semiconductor chip in the chip package.
13. The semiconductor package of claim 1 , wherein the chip package includes a plurality of semiconductor chips, each of the plurality of semiconductor chips having a penetration interconnection that is aligned with a penetration interconnection of an adjacent semiconductor chip.
14. The semiconductor package of claim 1 , wherein the chip package includes a plurality of directly stacked semiconductor chips.
15. The semiconductor package of claim 1 , wherein the chip package includes a plurality of semiconductor chips that are stacked so as not be spaced apart from each other.
16. The semiconductor package of claim 1 , wherein the chip package includes a plurality of semiconductor chips, and only an uppermost semiconductor chip of the plurality of semiconductor chips is connected to a bonding wire.
17. The semiconductor package of claim 2 , wherein the semiconductor chip group includes bumps disposed on its bottom face, each of the bumps of the semiconductor chip group being aligned with each through-hole via of the interposer.
18. The semiconductor package of claim 2 , wherein the chip package includes at least one semiconductor chip with penetration interconnections that are aligned with each of the through-hole vias of the interposer.
19. The semiconductor package of claim 1 , wherein a semiconductor chip of the semiconductor chip group that is closest to the interposer is not connected to a bonding wire.