Testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip
View Patent ↗Mechanisms are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SoC under test. The SoC under test generates actual test results data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.
1. A computer program product comprising a non-transitory computer useable storage device having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:
couple a model of a previously verified device to a model of a device under test via a communication interface model;
program the model of the previously verified device to store and execute a test program for applying one or more tests to the model of the device under test;
run the test program in the model of the previously verified device to thereby apply the one or more tests to the model of the device under test via the communication interface model; and
verify operation of the device under test based on results of running the test program, wherein:
the device under test and the previously verified device are both a system-on-a-chip (SoC), the model of the device under test is a SoC model under test,
the model of the previously verified device is a previously verified SoC model that is an earlier version of a same type of SoC as the SoC model under test,
the previously verified SoC model and the SoC model under test have a master/slave relationship,
the previously verified SoC model has a programmable memory model,
the model of the previously verified device is programmed to store and execute a test program by storing a test operating system in the memory model of the previously verified SoC model,
the previously verified SoC model acts as a master device in applying the one or more tests using the test operating system to the SoC model under test which acts as a slave device,
the test operating system applies the same test stimuli to one or more core models of the previously verified SoC model and to the SoC model under test, and
the test stimuli are stimuli that would be experienced by the device under test when interacting with one or more devices external to the device under test via a peripheral communication interface.
2. The computer program product of claim 1 , wherein the computer readable program further causes the computing device to:
apply the one or more tests to the previously verified SoC model to thereby generate expected test results.
3. The computer program product of claim 1 , wherein the SoC model under test generates actual test results based on the application of the one or more tests by the previously verified SoC model, and wherein the computer readable program further causes the computing device to:
compare the actual test results to the expected test results;
determine if there is a mismatch between the actual test results and the expected test results based on the comparison; and
output results of the comparison.
4. The computer program product of claim 3 , wherein the computer readable program causes the computing device to output the results of the comparison by one of displaying a notification or storing the results of the comparison in a data structure.
5. The computer program product of claim 1 , wherein the previously verified SoC model and the SoC model under test have a master/slave relationship, wherein the previously verified SoC model acts as a master device and the SoC model under test acts as a slave device.
6. An apparatus for testing a model of a device under test, comprising:
a processor; and
a memory coupled to the processor, wherein the memory is programmed with instructions, which when executed by the processor, causes the processor to:
couple a model of a previously verified device to a model of a device under test via a communication interface model;
program the model of the previously verified device to store and execute a test program for applying one or more tests to the model of the device under test;
run the test program in the model of the previously verified device to thereby apply the one or more tests to the model of the device under test via the communication interface model; and
verify operation of the device under test based on results of running the test program, wherein:
the device under test and the previously verified device are both a system-on-a-chip (SoC), the model of the device under test is a SoC model under test,
the model of the previously verified device is a previously verified SoC model that is an earlier version of a same type of SoC as the SoC model under test,
the previously verified SoC model and the SoC model under test have a master/slave relationship,
the previously verified SoC model has a programmable memory model,
the model of the previously verified device is programmed to store and execute a test program by storing a test operating system in the memory model of the previously verified SoC model,
the previously verified SoC model acts as a master device in applying the one or more tests using the test operating system to the SoC model under test which acts as a slave device,
the test operating system applies the same test stimuli to one or more core models of the previously verified SoC model and to the SoC model under test, and
the test stimuli are stimuli that would be experienced by the device under test when interacting with one or more devices external to the device under test via a peripheral communication interface.
7. The apparatus of claim 6 , wherein the instructions further cause the processor to:
apply the one or more tests to the previously verified SoC model to thereby generate expected test results.
8. The apparatus of claim 6 , wherein the SoC model under test generates actual test results based on the application of the one or more tests by the previously verified SoC model, and wherein the instructions further cause the processor to:
compare the actual test results to the expected test results;
determine if there is a mismatch between the actual test results and the expected test results based on the comparison; and
output results of the comparison.
9. The apparatus of claim 6 , wherein the previously verified SoC model and the SoC model under test have a master/slave relationship, wherein the previously verified SoC model acts as a master device and the SoC model under test acts as a slave device.