IP Library › Granted Patent US 8,026,151
Granted Patent B2
US 8,026,151 · App. 12/273,323 · Granted Sep 27, 2011

Method with high gapfill capability for semiconductor devices

Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
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Quick Facts
Patent No.
US 8,026,151
App. No.
12/273,323
Granted
Sep 27, 2011
Kind
B2
Abstract

A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Claims (21)

1. A method for processing semiconductor devices comprising:

forming a trench within a substrate, the trench having a total height;

filling 40% or less of the total height of the trench with a first oxide without any subsequent etching, the first oxide being filled using a spin-on process;

performing a first densification process on the first oxide within the trench;

depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench; and

performing a second densification process on the first and second oxides within the trench.

2. The method of claim 1 further comprising:

forming a stop layer overlying the substrate; and

forming a liner within the trench, the liner lining sidewalls and bottom of the trench.

3. The method of claim 2 further comprising:

performing a planarization process; and

removing the stop layer.

4. The method of claim 2 wherein the stop layer is silicon nitride.

5. The method of claim 3 further comprising removing a portion of the stop layer following the deposition of oxide within the trench using the HDP process.

6. The method of claim 1 further comprising forming a pad oxide layer overlying the substrate.

7. The method of claim 1 wherein the trench has a width of 0.10 μm of smaller.

8. The method of claim 1 wherein the trench has an aspect ratio of 5:1 or greater.

9. The method of claim 1 wherein one or more of the densification processes may be performed in an N2 and/or O2 ambient to produce an oxide having a compressive stress.

10. The method of claim 1 wherein one or more of the densification processes may be performed in an H2O ambient to produce an oxide having a tensile stress.

11. The method of claim 1 wherein the first densification process is performed at a temperature between 400-800 degrees C. for a duration between 30 seconds to 30 minutes.

12. The method of claim 1 wherein the second densification process is performed at a temperature between 850-1100 degrees C. for a duration between 30 seconds to 30 minutes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2010
From: ANG, TING CHEONG
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
Reel/Frame 024978/0827 →
Priority Claims (1)
CN 2006 1 0027042 · May 26, 2006 · national
Continuity (2)
Continuation 11539612 · Oct 6, 2006
Related Publication 20090075454A1 · Mar 19, 2009