Tunnel field effect transistor and method of manufacturing same
A TFET includes a source region ( 110, 210 ), a drain region ( 120, 220 ), a channel region ( 130, 230 ) between the source region and the drain region, and a gate region ( 140, 240 ) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
1. A tunnel field effect transistor comprising:
a substrate;
a source region over the substrate;
a drain region over the substrate;
a channel region between the source region and the drain region; and
a gate region adjacent to the channel region,
wherein:
the source region contains a first semiconducting material;
the channel region contains a second semiconducting material;
the second semiconducting material exhibits type-II band alignment with the first semiconducting material; and
the drain region contains a material having a charge neutrality level that lies above a bottom of its conduction band.
2. The tunnel field effect transistor of claim 1 wherein:
the source region and the channel region are arranged vertically above the substrate such that all of the source region is above all of the channel region.
3. The tunnel field effect transistor of claim 1 wherein:
the source region and the channel region are arranged horizontally above the substrate such that no portion of the source region is above all of the channel region and no portion of the channel region is above all of the source region.
4. The tunnel field effect transistor of claim 1 wherein:
the first semiconducting material and the second semiconducting material are lattice matched to each other.
5. The tunnel field effect transistor of claim 1 wherein:
the drain region contains a third semiconducting material;
the first semiconducting material is GaAs 0.5 Sb 0.5 ;
the second semiconducting material is In 0.53 Ga 0.47 As; and
the third semiconducting material is In 0.53 Ga 0.47 As.
6. The tunnel field effect transistor of claim 1 wherein:
a junction of the source region and the channel region comprises a tunneling junction of the tunnel field effect transistor;
the tunnel field effect transistor further comprises a delta layer at the tunneling junction;
the delta layer comprises a material that lowers a valence band offset and a band gap at the tunneling junction; and
the delta layer is fully strained.
7. The tunnel field effect transistor of claim 6 wherein:
the delta layer comprises GaAs 0.08 Sb 0.92 .
8. A method of manufacturing a tunnel field effect transistor, the method comprising:
providing a substrate;
selecting a first semiconducting material that has type-II band alignment with a second semiconducting material;
forming a first semiconducting region containing the first semiconducting material;
forming a second semiconducting region containing the second semiconducting material;
forming a third semiconducting region containing a third semiconducting material that has a charge neutrality level lying above a bottom of its conduction band;
depositing a gate insulator over at least a portion of at least the first semiconducting region;
forming a gate electrode over the gate insulator; and
forming a gate contact, a source contact, and a drain contact for the tunnel field effect transistor.
9. The method of claim 8 wherein:
the first semiconducting material comprises a first Group III material and a first Group V material;
the second semiconducting material comprises a second Group III material and a second Group V material; and
the third semiconducting material comprises a third Group III material and a third Group V material.
10. The method of claim 8 further comprising:
lattice matching the first semiconducting material and the second semiconducting material to each other.
11. The method of claim 8 wherein:
selecting the first semiconducting material comprises selecting GaAs 0.5 Sb 0.5 ;
the second semiconducting material comprises In 0.53 Ga 0.47 As; and
the third semiconducting material comprises In 0.53 Ga 0.47 As.
12. A tunnel field effect transistor comprising:
a substrate;
a source region over the substrate;
a drain region over the substrate;
a channel region between the source region and the drain region; and
a gate region adjacent to the channel region,
wherein:
the source region contains a first semiconducting material;
the channel region contains a second semiconducting material;
the second semiconducting material exhibits type-II band alignment with the first semiconducting material; and
the first semiconducting material and the second semiconducting material are lattice matched to each other.
13. The tunnel field effect transistor of claim 12 , wherein:
the source region and the channel region are arranged vertically above the substrate such that all of the source region is above all of the channel region.
14. The tunnel field effect transistor of claim 12 , wherein:
the source region and the channel region are arranged horizontally above the substrate such that no portion of the source region is above all of the channel region and no portion of the channel region is above all of the source region.
15. The tunnel field effect transistor of claim 12 , wherein:
the drain region contains a third semiconducting material;
the first semiconducting material is GaAs 0.5 Sb 0.5 ;
the second semiconducting material is In 0.53 Ga 0.47 As; and
the third semiconducting material is In 0.53 Ga 0.47 As.
16. The tunnel field effect transistor of claim 12 , wherein:
a junction of the source region and the channel region comprises a tunneling junction of the tunnel field effect transistor;
the tunnel field effect transistor further comprises a delta layer at the tunneling junction;
the delta layer comprises a material that lowers a valence band offset and a band gap at the tunneling junction; and
the delta layer is fully strained.
17. The tunnel field effect transistor of claim 12 , wherein:
the delta layer comprises GaAs 0.08 Sb 0.92 .
18. A tunnel field effect transistor comprising:
a substrate;
a source region over the substrate;
a drain region over the substrate;
a channel region between the source region and the drain region; and
a gate region adjacent to the channel region,
wherein:
the source region contains GaAs 0.5 Sb 0.5 ;
the channel region contains In 0.53 Ga 0.47 As; and
the drain region contains In 0.53 Ga 0.47 As.
19. The tunnel field effect transistor of claim 18 , wherein:
the source region and the channel region are arranged vertically above the substrate such that all of the source region is above all of the channel region.
20. The tunnel field effect transistor of claim 18 , wherein:
the source region and the channel region are arranged horizontally above the substrate such that no portion of the source region is above all of the channel region and no portion of the channel region is above all of the source region.
21. The tunnel field effect transistor of claim 18 , wherein:
a junction of the source region and the channel region comprises a tunneling junction of the tunnel field effect transistor;
the tunnel field effect transistor further comprises a delta layer at the tunneling junction;
the delta layer comprises a material that lowers a valence band offset and a band gap at the tunneling junction; and
the delta layer is fully strained.
22. The tunnel field effect transistor of claim 18 , wherein:
the delta layer comprises GaAs 0.08 Sb 0.92 .
23. A tunnel field effect transistor comprising:
a substrate;
a source region over the substrate;
a drain region over the substrate;
a channel region between the source region and the drain region; and
a gate region adjacent to the channel region,
wherein:
the source region contains a first semiconducting material;
the channel region contains a second semiconducting material;
the second semiconducting material exhibits type-II band alignment with the first semiconducting material;
a junction of the source region and the channel region comprises a tunneling junction of the tunnel field effect transistor;
the tunnel field effect transistor further comprises a delta layer comprising GaAs 0.08 Sb 0.92 at the tunneling junction;
the delta layer comprises a material that lowers a valence band offset and a band gap at the tunneling junction; and
the delta layer is fully strained.
24. A method of manufacturing a tunnel field effect transistor, the method comprising:
providing a substrate;
selecting a first semiconducting material that has type-II band alignment with a second semiconducting material;
forming a first semiconducting region containing the first semiconducting material;
forming a second semiconducting region containing the second semiconducting material;
forming a third semiconducting region containing a third semiconducting material;
depositing a gate insulator over at least a portion of at least the first semiconducting region;
forming a gate electrode over the gate insulator;
forming a gate contact, a source contact, and a drain contact for the tunnel field effect transistor; and
lattice matching the first semiconducting material and the second semiconducting material to each other.
25. A method of manufacturing a tunnel field effect transistor, the method comprising:
providing a substrate;
forming a first semiconducting region containing GaAs 0.5 Sb 0.5 ;
forming a second semiconducting region containing In 0.53 Ga 0.47 As;
forming a third semiconducting region containing In 0.53 Ga 0.47 As;
depositing a gate insulator over at least a portion of at least the first semiconducting region;
forming a gate electrode over the gate insulator; and
forming a gate contact, a source contact, and a drain contact for the tunnel field effect transistor.