Erase cycle counter usage in a memory device
Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
1. A method of operating a memory device, comprising:
maintaining an erase cycle counter value corresponding to each memory block of a plurality of memory blocks of the memory device where each memory block comprises a plurality of memory cells;
storing each erase cycle counter value in a memory block of the plurality of memory blocks which is different than its corresponding memory block; and
adjusting a programming voltage applied to one or more memory cells of a particular block of memory cells in response to the erase cycle counter value corresponding to the particular block;
wherein storing each erase cycle counter value further comprises storing each erase cycle counter value in a page of a memory block.
2. A method of operating a memory device, comprising:
maintaining an erase cycle counter value corresponding to each memory block of a plurality of memory blocks of the memory device where each memory block comprises a plurality of memory cells;
storing each erase cycle counter value in a memory block of the plurality of memory blocks which is different than its corresponding memory block;
adjusting a programming voltage applied to one or more memory cells of a particular block of memory cells in response to the erase cycle counter value corresponding to the particular block; and
translating erase cycle count data to SLC data to be stored in memory cells configured to accept MLC data.
3. A method of operating a memory device, comprising:
maintaining an erase cycle counter value corresponding to each memory block of a plurality of memory blocks of the memory device where each memory block comprises a plurality of memory cells;
storing each erase cycle counter value in a memory block of the plurality of memory blocks which is different than its corresponding memory block;
storing a redundant erase cycle counter value as complementary data to each stored erase cycle counter value; and
adjusting a programming voltage applied to one or more memory cells of a particular block of memory cells in response to the erase cycle counter value corresponding to the particular block.
4. A method of operating a memory device, comprising:
maintaining an erase cycle counter value for each memory block of a plurality of memory blocks of the memory device where each memory block comprises a plurality of memory cells;
storing each erase cycle counter value in a corresponding memory block;
storing a redundant erase cycle counter value for each stored erase cycle counter value; and
adjusting a programming voltage applied to one or more memory cells of a particular block of memory cells in response to the erase cycle counter value corresponding to the particular block;
wherein storing redundant erase cycle counter values comprises storing redundant erase cycle counter values as complementary data to the erase cycle counter values.
5. The method of claim 4 , further comprising performing an erase cycle counter value error detection operation.
6. The method of claim 5 , further comprising performing a erase cycle counter value error recovery operation.
7. The method of claim 6 , wherein performing an erase cycle counter value error recovery operation comprises determining an estimated erase cycle counter value as a function of one or more erase cycle counter values stored in one or more memory blocks of the memory device other than the memory block associated with the erroneous erase cycle counter value.
8. The method of claim 7 , wherein determining the estimated erase cycle counter value further comprises determining the estimated erase cycle counter value to be the maximum value of the one or more erase cycle counter values stored in the one or more other memory blocks of the memory device.
9. The method of claim 7 , wherein determining the estimated erase cycle counter value further comprises determining the estimated erase cycle counter value to be an average value of the one or more erase cycle counter values stored in the one or more other memory blocks of the memory device.
10. A method of operating a memory device, comprising:
maintaining an erase cycle counter value corresponding to each memory block of a plurality of memory blocks of the memory device where each memory block comprises a plurality of memory cells;
storing each erase cycle counter value in a memory block of the plurality of memory blocks which is different than its corresponding memory block; and
adjusting a programming voltage applied to one or more memory cells of a particular block of memory cells in response to the erase cycle counter value corresponding to the particular block;
wherein maintaining the erase cycle counter value for each memory block of the plurality of memory blocks further comprises incrementing the erase cycle counter value corresponding to a particular memory block in response to performing an erase operation on the particular memory block.
11. The method of claim 10 , wherein incrementing the erase cycle counter value corresponding to a particular memory block in response to performing an erase operation further comprises incrementing the erase cycle counter value by a number of erase pulses applied to the particular memory block during the erase operation.
12. A method of operating a memory device, comprising:
selecting a memory block of the memory device for erasure where the selected memory block is selected from a plurality of memory blocks each memory block comprising one or more memory cells;
performing a read operation of an erase cycle counter value corresponding to the selected memory block;
performing an erase operation on the selected memory block;
updating the read erase cycle counter value in response to the erase operation performed on the selected memory block;
storing the updated erase cycle counter value corresponding to the selected memory block in a memory block of the memory device other than the selected memory block; and
determining an initial programming voltage to apply to one or more memory cells of the selected memory block where the initial programming voltage is determined in response to the erase cycle counter value corresponding to the selected memory block;
wherein storing the updated erase cycle counter value corresponding to the selected memory block in the memory device further comprises storing the updated erase cycle counter value following an erase operation performed on the selected memory block.
13. A method of operating a memory device, comprising:
selecting a memory block of the memory device for erasure where the selected memory block is selected from a plurality of memory blocks each memory block comprising one or more memory cells;
performing a read operation of an erase cycle counter value corresponding to the selected memory block;
performing an erase operation on the selected memory block;
updating the read erase cycle counter value in response to the erase operation performed on the selected memory block;
storing the updated erase cycle counter value corresponding to the selected memory block in a memory block of the memory device other than the selected memory block;
determining an initial programming voltage to apply to one or more memory cells of the selected memory block where the initial programming voltage is determined in response to the erase cycle counter value corresponding to the selected memory block; and
storing the value of the determined initial programming voltage in the selected memory block.
14. A memory device, comprising:
a plurality of memory cells arranged in a plurality of erase blocks each erase block storing an erase cycle counter value and a redundant erase cycle counter value, where the erase cycle counter value is representative of a number of erase cycles performed on that erase block; and
control circuitry, wherein the control circuitry is configured to determine an initial programming voltage to apply to memory cells of a selected erase block, update the erase cycle counter value and the redundant erase cycle counter value for the selected erase block in response to an erase operation performed on the selected erase block, and store the updated erase cycle counter value and the updated redundant erase cycle counter value in the selected erase block;
wherein the determined initial programming voltage is based upon the erase cycle counter value stored in the selected erase block; and
wherein each redundant erase cycle counter value comprises a complimentary data value of its corresponding erase cycle counter value.
15. The memory device of claim 14 , wherein the selected erase block is configured to contain MLC memory cells and the control circuitry is further configured to store the updated erase cycle counter value in the MLC memory cells of the selected erase block as SLC data.
16. The memory device of claim 14 , wherein the control circuitry is further configured to determine one of a valid state and an invalid state of the erase cycle counter value stored in the selected erase block.
17. The memory device of claim 16 , wherein the control circuitry is further configured to generate an estimated erase cycle counter value corresponding to the selected erase block in response to an invalid state determination of the erase cycle counter value.
18. The memory device of claim 14 , wherein the control circuitry is further configured to perform a program operation on one or more memory cells of the selected erase block where a first applied programming voltage pulse voltage for the program operation is the determined initial programming voltage.
19. The memory device of claim 14 , wherein the control circuitry is further configured to store the determined initial programming voltage in the selected erase block.
20. The memory device of claim 14 , wherein the control circuitry is further configured to perform a erase cycle counter value error detection operation on the erase cycle counter value stored in the selected erase block.
21. An electronic system, comprising:
a host device; and
a memory device coupled to the host, the memory device comprising:
an array of memory cells arranged in a plurality of erase blocks each erase block storing an erase cycle counter value representative of a number of erase cycles performed on that erase block and a redundant erase cycle counter value comprising complementary data of the erase cycle counter value; and
control circuitry, wherein the control circuitry is configured to read an erase cycle counter value stored in a selected erase block of the plurality of erase blocks, determine an initial programming voltage to apply to memory cells of the selected erase block where the initial programming voltage is determined based upon the erase cycle counter value read from the selected erase block, update the erase cycle counter value and the redundant erase cycle counter value in response to an erase operation performed on the selected erase block and store the updated erase cycle counter value and redundant erase cycle counter value in the selected erase block.