Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
View Patent ↗A semiconductor device has dual-molded semiconductor die mounted to opposite sides of a build-up interconnect structure. A first semiconductor die is mounted to a temporary carrier. A first encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the first encapsulant and first semiconductor die. The first interconnect structure is electrically connected to first contact pads of the first semiconductor die. A plurality of conductive pillars is formed over the first interconnect structure. A second semiconductor die is mounted between the conductive pillars to the first interconnect structure. A second encapsulant is deposited over the second semiconductor die. A second interconnect structure is formed over the second encapsulant. The second interconnect structure is electrically connected to the conductive pillars and first and second semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a temporary carrier;
mounting a first semiconductor die with first contact pads oriented to the temporary carrier;
depositing a first encapsulant over the first semiconductor die and temporary carrier;
removing the temporary carrier;
forming a first interconnect structure over a first surface of the first encapsulant and first semiconductor die, the first interconnect structure being electrically connected to the first contact pads of the first semiconductor die;
forming a plurality of first conductive pillars over the first interconnect structure;
mounting a second semiconductor die between the first conductive pillars with second contact pads oriented to the first interconnect structure;
depositing a second encapsulant over the second semiconductor die and first interconnect structure; and
forming a second interconnect structure over the second encapsulant, the second interconnect structure being electrically connected to the first conductive pillars and first and second contact pads of the first and second semiconductor die.
2. The method of claim 1 , further including:
forming a plurality of second conductive pillars over the temporary carrier prior to forming the first encapsulant; and
forming a third interconnect structure over a second surface of the first encapsulant opposite the first surface of the first encapsulant, the third interconnect structure being electrically connected to the second conductive pillars and first interconnect structure.
3. The method of claim 1 , wherein forming the second interconnect structure includes:
forming a conductive layer over the second encapsulant; and
forming bumps over the conductive layer and first conductive pillars.
4. The method of claim 1 , wherein the first conductive pillars extend from the second encapsulant.
5. The method of claim 1 , wherein the first conductive pillars are recessed with respect to a portion of the second encapsulant over the second semiconductor die.
6. The method of claim 1 , further including planarizing the first encapsulant to expose a back surface of the first semiconductor die opposite the first contact pads.
7. The method of claim 1 , further including planarizing the second encapsulant to expose a back surface of the second semiconductor die opposite the second contact pads.
8. A method of making a semiconductor device, comprising:
providing a first semiconductor component;
depositing a first encapsulant over the first semiconductor component;
forming a first interconnect structure over a first surface of the first encapsulant and first semiconductor component, the first interconnect structure being electrically connected to the first semiconductor component;
mounting a second semiconductor component to the first interconnect structure;
depositing a second encapsulant over the second semiconductor component and first interconnect structure; and
forming a second interconnect structure over the second encapsulant, the second interconnect structure being electrically connected to the first and second semiconductor components.
9. The method of claim 8 , further including:
forming a plurality of conductive pillars over the first interconnect structure prior to depositing the second encapsulant; and
depositing the second encapsulant over the second semiconductor component and first interconnect structure and around the conductive pillars.
10. The method of claim 9 , wherein the conductive pillars extend from the second encapsulant.
11. The method of claim 8 , further including forming a conductive via through the second encapsulant.
12. The method of claim 8 , further including:
forming a plurality of conductive pillars adjacent to the first semiconductor component prior to forming the first encapsulant; and
forming a third interconnect structure over a second surface of the first encapsulant opposite the first surface of the first encapsulant, the third interconnect structure being electrically connected to the conductive pillars and first interconnect structure.
13. The method of claim 8 , wherein forming the second interconnect structure includes:
forming a conductive layer over a second surface of the first encapsulant opposite the first surface of the first encapsulant; and
forming bumps over the conductive layer.
14. The method of claim 8 , further including forming a shielding layer over the first semiconductor component or second semiconductor component.
15. A method of making a semiconductor device, comprising:
providing a first semiconductor component;
depositing a first encapsulant over the first semiconductor component;
forming a first interconnect structure over a first surface of the first encapsulant and first semiconductor component, the first interconnect structure being electrically connected to the first semiconductor component;
mounting a second semiconductor component to the first interconnect structure;
depositing a second encapsulant over the second semiconductor component and first interconnect structure; and
forming a second interconnect structure over the second encapsulant, the second interconnect structure being electrically connected to the first and second semiconductor components.
16. The method of claim 15 , further including:
forming a plurality of conductive pillars adjacent to the first semiconductor component prior to forming the first encapsulant; and
forming a third interconnect structure over a second surface of the first encapsulant opposite the first surface of the first encapsulant, the third interconnect structure being electrically connected to the conductive pillars and first interconnect structure.
17. The method of claim 15 , further including forming a conductive via through the second encapsulant.
18. The method of claim 15 , further including:
forming a plurality of conductive pillars over the first interconnect structure prior to forming the second encapsulant; and
depositing the second encapsulant over the second semiconductor component and first interconnect structure and around the conductive pillars.
19. The method of claim 18 , wherein forming the second interconnect structure includes:
forming a conductive layer over a second surface of the first encapsulant opposite the first surface of the first encapsulant; and
forming bumps over the conductive layer and conductive pillars.
20. The method of claim 15 , wherein the second semiconductor component is a discrete semiconductor component.