Pitch multiplied mask patterns for isolated features
Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross, e.g., are orthogonal to, the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with material, e.g., conductive material, to form conductive contacts.
1. A mask pattern overlying a partially fabricated integrated circuit, comprising:
a first plurality of mandrels on a first level;
a first plurality of spacers disposed at sides of mandrels of the first plurality of mandrels;
a second plurality of mandrels on a second level above the first level, wherein each mandrel of the second plurality of mandrels contacts multiple mandrels of the first plurality of mandrels; and
a second plurality of elongated spacers disposed at sides of mandrels of the second plurality of mandrels.
2. The mask pattern of claim 1 , wherein the first and the second plurality of mandrels are formed of a same mandrel material.
3. The mask pattern of claim 2 , wherein the mandrel material is a reflowable material.
4. The mask pattern of claim 2 , wherein the first and the second plurality of spacers are formed of different spacer materials.
5. The mask pattern of claim 1 , wherein mandrels of the first plurality of mandrels have widths of about 70 nm or less.
6. The mask pattern of claim 1 , wherein mandrels of the second plurality of mandrels have widths of about 70 nm or less.
7. The mask pattern of claim 1 , further comprising an intermediate hard mask layer disposed between the first level and the partially fabricated integrated circuit.
8. The mask pattern of claim 7 , wherein the intermediate hard mask layer comprises amorphous carbon.
9. The mask pattern of claim 1 , wherein the partially fabricated integrated circuit is a partially fabricated memory device.
10. A mask pattern overlying a partially fabricated integrated circuit, comprising:
a first plurality of elongated spacers on a first level; and
a second plurality of elongated spacers on a second level, wherein spacers of first plurality of spacers and spacers of the second plurality of spacers extend at an angle of about 30-90° relative to one another.
11. The mask pattern of claim 10 , wherein each of the spacers is a closed loop.
12. The mask pattern of claim 10 , further comprising a dielectric layer underlying the first and the second levels.
13. The mask pattern of claim 12 , wherein the dielectric layer comprises voids, the voids aligning with openings delimited by spacer material on each of the first and the second levels.
14. The mask pattern of claim 12 , wherein the angle is about 90°.
15. The mask pattern of claim 10 , wherein spacers of the first plurality of elongated spacers are enclosed within a planarization layer, wherein spacers of the second plurality of elongated spacers sit on a surface of the planarization layer.
16. The mask pattern of claim 15 , wherein the planarization layer comprises amorphous carbon.
17. The mask pattern of claim 16 , wherein spacers of the first plurality of elongated spacers comprises silicon.
18. The mask pattern of claim 17 , wherein spacers of the second plurality of elongated spacers comprises an oxide.
19. The mask pattern of claim 10 , wherein spacers of the first and the second plurality of spacers have sub-lithographic widths.
20. The mask pattern of claim 10 , wherein spacers of the first and the second plurality of spacers have widths of about 20-80 nm.
21. The mask pattern of claim 10 , wherein spacers of the first and the second plurality of spacers are pitch-multiplied.
22. The mask pattern of claim 10 , wherein spacers of the first plurality of spacers are substantially parallel.
23. The mask pattern of claim 22 , wherein spacers of the second plurality of spacers are substantially parallel.
24. The mask pattern of claim 23 , wherein spacers of the second plurality of spacers are substantially uniformly spaced.
25. The mask pattern of claim 22 , wherein spacers of the first plurality of spacers are substantially uniformly spaced.