Serial interface device built-in self test
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
1. A built-in self test circuit comprising:
a pattern generator coupled to a port under test for generating a first test pattern to test a port under test;
an elastic buffer coupled to the port under test for receiving a test result pattern from the port under test, wherein the test result pattern is gotten according to the first test pattern;
a symbol detector coupled to the elastic buffer for detecting whether a starting symbol is found in the test result pattern; wherein a second test pattern which is substantially identical to the first test pattern is generated while the starting symbol is detected; and
a comparison unit for comparing the test result pattern and the second test pattern.
2. The built-in self test circuit of claim 1 further comprising a counter coupled to the comparison unit for accumulating how many different symbols exist between the test result pattern and the second test pattern.
3. The built-in self test circuit of claim 2 wherein the counter is further coupled to an error rate detecting circuit for figuring out an error rate of the port under test.
4. The built-in self test circuit of claim 1 wherein the second test pattern is generated by the pattern generator.
5. The built-in self test circuit of claim 1 the built-in self test circuit further comprises a second pattern generator for generating the second test pattern.
6. The built-in self test circuit of claim 1 further comprising a drive circuit for driving the pattern generator.
7. The built-in self test circuit of claim 1 wherein the built-in self test circuit further comprises a counter coupled to the comparison unit for estimating a bit error rate of the port under test.
8. The built-in self test circuit of claim 1 wherein the built-in self test circuit is applies to a serial interface device.
9. The built-in self test circuit of claim 1 wherein the built-in self test circuit is applies to a USB 3.0 device.
10. The built-in self test circuit of claim 1 wherein the built-in self test circuit is applies to a SATA device.
11. A self test method for testing, the method comprising:
utilizing a first test pattern to test a port under test to get a test result pattern according to the first test pattern;
detecting whether a starting symbol is in the test result pattern;
generating a second test pattern while the starting symbol is detected, wherein second test pattern is substantially identical to the first test pattern; and
comparing the test result pattern and the second test pattern.
12. The method of claim 11 further comprising counting how many different symbols exist between the test result pattern and the second test pattern, and estimating an error rate of the port under test.
13. The method of claim 11 wherein the self test is applied to the port under test of a serial interface device.
14. The method of claim 11 wherein the self test is applied to the port under test of a USB 3.0 device.
15. The method of claim 11 wherein the self test is applied to the port under test of a SATA device.