Multicore processor having storage for core-specific operational data

1. A method, comprising:

storing in a readable non-volatile memory of a multicore processor integrated circuit device, that stores an identification of the multicore processor integrated circuit device, information expressive of at least one determined operating characteristic for each individual one of a plurality of processor cores that comprise the multicore processor integrated circuit device; and

during one of system boot or initial program load time, reading the information from the non-volatile memory and loading machine state registers of the multicore processor integrated circuit device with the information expressive of the at least one of the determined operating characteristics for each individual one of the plurality of processor cores, the machine state registers being connected with an interface of the multicore processor integrated circuit device for being interrogated by a supervisor program that identifies system resources for an operating system for scheduling program tasks to individual ones of the processor cores.

2. The method of claim 1 , where the information is indicative of a maximum operating frequency for each of the plurality of processor cores.

3. The method of claim 1 , where the information is indicative of leakage power for each of the plurality of processor cores.

4. An integrated circuit, comprising:

a plurality of processor cores;

an interface to circuitry external to the integrated circuit;

a readable non-volatile memory that stores information expressive of at least one operating characteristic of each individual one of the plurality of processor cores; and

machine state registers configured to be loaded during one of system boot and initial program load time with the information expressive of the at least one of the determined operating characteristics for each individual one of the plurality of processor cores, the machine state registers being connected with said interface for being interrogated by a supervisor program that identifies system resources for an operating system for scheduling program tasks to individual ones of the processor cores.

5. The integrated circuit of claim 4 , where the information is indicative of a maximum operating frequency of each of the plurality of processor cores.

6. The integrated circuit of claim 4 , where the information is indicative of leakage power of each of the plurality of processor cores.

7. The integrated circuit of claim 4 , where the memory also stores electronic chip identification information.

8. The integrated circuit of claim 5 , where each of said plurality of processor cores is provided, during operation, with a clock signal having a frequency that is less than the maximum operating frequency.

9. A data processing system, comprising:

a multicore processor integrated circuit comprised of a plurality of processor cores, a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency of each individual one of the plurality of processor cores, an interface to circuitry external to the multicore processor integrated circuit, and machine state registers configured to be loaded during one of system boot and initial program load time with the information indicative of at least a maximum operating frequency of each individual one of the plurality of processor cores, the machine state registers being connected with said interface and readable through said interface; and

a scheduler coupled to an operating system and to the multicore processor integrated circuit via said interface, said scheduler responsive at least in part to information read from the machine state registers via said interface to schedule the execution of threads to individual ones of the processor cores.

10. The data processing system of claim 9 , where the information is further indicative of leakage power for each of the plurality of processor cores.

11. The data processing system of claim 10 , where said scheduler is responsive at least in part to the information indicative of leakage power for selectively placing one or more of the processor cores in a reduced power consumption mode of operation.

12. The data processing system of claim 9 , where said scheduler is further responsive at least in part to dynamic instruction reordering, standing pipeline queue depths, known contents of a given processor core's cache memory and an urgency of a given processor core's output.

13. The data processing system of claim 9 , where each of said plurality of processor cores is provided, during operation, with a clock signal having a frequency that is less than the maximum operating frequency.

14. A method to operate a data processing system, comprising:

providing a multicore processor integrated circuit comprised of a plurality of processor cores and a readable non-volatile memory embodied as a bank of electrical fuses that store information, determined during a testing operation, that is indicative of at least a maximum operating frequency of each individual one of the plurality of processor cores, said multicore processor integrated circuit further comprised of an interface to circuitry external to the multicore processor integrated circuit, and machine state registers configured to be loaded from the bank of electrical fuses during one of system boot and initial program load time with the information indicative of at least a maximum operating frequency of each individual one of the plurality of processor cores, the machine state registers being connected with said interface and readable through said interface; and

operating a scheduler coupled to an operating system and to the multicore processor integrated circuit via said interface, said scheduler responsive at least in part to information read from the machine state registers via said interface to schedule the execution of threads to individual ones of the processor cores.

15. The method of claim 14 , where the information is further indicative of leakage power for each of the plurality of processor cores.

16. The method of claim 15 , further comprising operating said scheduler, in response at least in part to the information indicative of leakage power, for selectively placing one or more of the processor cores in a reduced power consumption mode of operation.

17. The method of claim 14 , where said scheduler operation is directed by program instructions stored in a memory medium, and further responds to at least one of dynamic instruction reordering, standing pipeline queue depths, known contents of a given processor core's cache memory and an urgency of a given processor core's output.

18. The method of claim 14 , where the information indicative of at least the maximum operating frequency of each individual one of the plurality of processor cores is programmed into said bank of electrical fuses during a same operation that stores an electronic chip identification (ECID) into said bank of electrical fuses.