Integrated circuit having a filler standard cell
An integrated circuit includes a functional block having a plurality of standard cells. The plurality of standard cells includes a plurality of functional standard cells and a filler standard cell. Each functional standard cell of the plurality of functional standard cells has a rectangular boundary. The filler standard cell has a rectangular boundary adjacent to at least one of the functional standard cells. The filler standard cell is selectable between a first state and a second state. The filler standard cell is non-functional in the first state. The filler standard cell has functional test structures coupled to a first metal layer in the second state. This allows for test structures helpful in analyzing functionality of circuit features such as transistors without requiring additional space on the integrated circuit.
1. An integrated circuit, comprising:
a functional block comprising a plurality of standard cells, wherein:
the plurality of standard cells comprise a plurality of functional standard cells and a filler standard cell;
each functional standard cell of the plurality of functional standard cells have a rectangular boundary;
the filler standard cell has a rectangular boundary adjacent to at least one of the plurality of functional standard cells;
the filler standard cell is selectable between a first state and a second state;
the filler standard cell is non-functional in the first state; and
the filler standard cell has functional test structures coupled to a first metal layer in the second state; and
a probe pad connected to the filler standard cell in the second state, wherein the probe pad is spaced from the filler standard cell in the second state.
2. The integrated circuit of claim 1 , wherein the first metal layer has a first configuration for the first state and a second configuration different from the first configuration for the second state.
3. The integrated circuit of claim 1 , wherein the functional test structures comprises a plurality of transistors.
4. The integrated circuit of claim 1 , wherein the filler standard cell in the first state comprises a dummy feature, wherein the dummy feature comprises a polysilicon dummy gate.
5. The integrated circuit of claim 4 , wherein the dummy feature further comprises a first active region spaced away from the polysilicon dummy gate on a first side of the polysilicon dummy gate and a second active region spaced away from the polysilicon dummy gate on a second side of the polysilicon dummy gate.
6. The integrated circuit of claim 1 , wherein the filler standard cell in the first state has a ground metal line that crosses the filler standard cell in a first direction and a power metal line that crosses the filler standard cell in the first direction.
7. The integrated circuit of claim 1 , wherein the functional block is for performing a logic function.
8. The integrated circuit of claim 1 , wherein the functional block is for performing an analog function.
9. The integrated circuit of claim 1 , wherein the functional block has a boundary that is rectangular.
10. The integrated circuit of claim 1 , wherein the integrated circuit has a first contact pattern for the first state and a second contact pattern different from the first contact pattern for the second state.
11. The integrated circuit of claim 1 , wherein the functional block further comprises a second filler standard cell having a first state in which the second filler standard cell is non-functional and a second state in which the second filler standard cell is connected by the first metal layer in a manner different from that in which the first metal layer is connected in the first state of the second filler standard cell.
12. An integrated circuit, comprising:
a logic block having a plurality of logic standard cells and a filler standard cell, wherein:
each of the plurality of logic standard cells is rectangular;
the filler standard cell is rectangular and adjacent to at least one of the plurality of logic standard cells;
the filler standard cell is programmable by a first metal layer;
the first metal layer in a first configuration causes the filler standard cell to be in a first state and the first metal layer in a second configuration causes the filler standard cell to be in a second state;
in the first state the filler standard cell is non-functional; and
in the second state the filler standard cell has functional test transistors coupled to probe pads.
13. The integrated circuit of claim 12 , wherein the probe pads are spaced away from the filler standard cell in the second state and the filler standard cell has a contact pattern in the second state that is different from a contact pattern in the first state.
14. An integrated circuit, comprising:
a functional block including a plurality of standard cells, wherein:
the plurality of standard cells comprise a plurality of functional standard cells having rectangular boundaries and a filler standard cell having a rectangular boundary adjacent to at least one of the plurality of functional standard cells;
the filler standard cell is selectable between a non- functional first state and a second state;
the filler standard cell has functional test structures coupled to a first metal layer in the second state;
the filler standard cell in the first state has a dummy feature that comprises a polysilicon dummy gate and a first active region spaced from the polysilicon dummy gate on a first side of the polysilicon dummy gate and a second active region spaced from the polysilicon dummy gate on a second side of the polysilicon dummy gate.