IP Library Granted Patent US 8,067,271
Granted Patent B2
US 8,067,271 · App. 11/532,509 · Granted Nov 29, 2011

Integrated circuit package system with encapsulation lock

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Quick Facts
Patent No.
US 8,067,271
App. No.
11/532,509
Granted
Nov 29, 2011
Kind
B2
Abstract

An integrated circuit package system is provided including forming an external interconnect and a tie bar, forming a lead tip and a lead body of the external interconnect, forming a hole in the external interconnect, forming a slot in the tie bar, connecting an integrated circuit die and the external interconnect, and molding the external interconnect and the tie bar with the slot and the hole filled.

Claims (44)

1. A method of making an integrated circuit package system comprising:

forming an external interconnect, a paddle, and a tie bar, the external interconnect having a lead tip and a leadbody with a paddle top surface of the paddle below a lead top surface planar across extents of the lead tip, and a paddle bottom surface in a same horizontal plane as a lead bottom surface of the lead body;

forming a through hole in the lead tip of the external interconnect;

forming a longitudinal slot along a length-wise dimension of the tie bar;

connecting an integrated circuit die and the external interconnect with a portion of the longitudinal slot under the integrated circuit die; and

molding the external interconnect and the tie bar with an encapsulation through the through hole integral with a layer of the encapsulation above the through hole and a layer of the encapsulation below the through hole, the encapsulation filling the slot.

2. The method as claimed in claim 1 wherein the connecting includes attaching a solder bump between the integrated circuit die and the lead tip.

3. The method as claimed in claim 1 wherein the connecting includes attaching a bond wire between the integrated circuit die and the lead tip.

4. The method as claimed in claim 1 further comprising:

forming a recess in the lead body from a lead body top surface; and

wherein the molding fills the recess.

5. The method as claimed in claim 1 wherein the molding includes covering the integrated circuit die.

6. A method of making an integrated circuit package system comprising:

forming an external interconnect, a paddle, and a tie bar, the external interconnect having a lead tip and a leadbody with a paddle top surface of the paddle below a lead top surface planar across extents of the lead tip, and a paddle bottom surface in a same horizontal plane as a lead bottom surface of the lead body;

forming a through hole in the lead tip;

forming a longitudinal slot along a length-wise dimension of the tie bar;

connecting an integrated circuit die, over the paddle, and the external interconnect with a portion of the longitudinal slot under the integrated circuit die; and

molding the external interconnect and the tie bar with an encapsulation through the through hole integral with a layer of the encapsulation above the through hole and a layer of the encapsulation below the through hole, the encapsulation filling the slot.

7. The method as claimed in claim 6 wherein forming the tie bar and the paddle includes connecting the tie bar and the paddle.

8. The method as claimed in claim 6 wherein forming the lead tip and the lead body of the external interconnect includes half etching the external interconnect to form the lead tip and the lead body.

9. The method as claimed in claim 6 wherein molding the external interconnect includes exposing the lead body at a lead body bottom surface.

10. The method as claimed in claim 6 wherein the molding includes covering the paddle.

11. An integrated circuit package system comprising:

a paddle having a paddle top surface and a paddle bottom surface;

an external interconnect having a lead tip with a through hole and a lead body with the paddle top surface below a lead top surface planar across extents of the lead tip, and the paddle bottom surface in a same horizontal plane as a lead bottom surface of the lead body;

a tie bar having a longitudinal slot along a length wise dimension of the tie bar;

an internal interconnect between an integrated circuit die and the external interconnect with a portion of the longitudinal slot under the integrated circuit die; and

an encapsulation to cover the external interconnect and the tie bar with the encapsulation through the through hole integral with a layer of the encapsulation above the through hole and a layer of the encapsulation below the through hole, the encapsulation filling the slot.

12. The system as claimed in claim 11 wherein the internal interconnect is a solder bump between the integrated circuit die and the lead tip.

13. The system as claimed in claim 11 wherein the internal interconnect is a bond wire between the integrated circuit die and the lead tip.

14. The system as claimed in claim 11 further comprising:

a recess in the lead body from a lead body top surface; and

wherein the encapsulation is a filler in the recess.

15. The system as claimed in claim 11 wherein the encapsulation is a cover for the integrated circuit die.

16. The system as claimed in claim 11 wherein:

the external interconnect is a lead having the lead tip and the lead body;

the tie bar is next to the external interconnect;

the slot is another through hole in the tie bar;

the internal interconnect is on an active side of the integrated circuit die and connected to the external interconnect; and

the encapsulation is cover for the external interconnect and the tie bar and a filler in the slot and the hole filled.

17. The system as claimed in claim 16 wherein the tie bar is connected to the paddle.

18. The system as claimed in claim 16 wherein the external interconnect having the lead tip and the lead body has a lead tip bottom surface above a lead body bottom surface.

19. The system as claimed in claim 16 wherein the encapsulation has the lead body at a lead body bottom surface exposed.

20. The system as claimed in claim 16 wherein the encapsulation is a cover for the paddle.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2006
From: DO, BYUNG TAI; YANG, SUNG UK
To: STATS CHIPPAC LTD.
Reel/Frame 018266/0567 →