Method of making nonvolatile memory device containing carbon or nitrogen doped diode

1. A method of making a nonvolatile memory device, comprising:

forming a first electrode;

forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode;

intentionally doping at least a portion of the diode with at least one of nitrogen or carbon, wherein a concentration of carbon in the diode is lower than 1×10 21 cm −3 and a concentration of nitrogen in the diode is lower than 1×10 21 cm −3 , and wherein the diode has a leakage current of less than 4×10 −10 A at −5.5 V in a high resistivity, reset state; and

forming a second electrode over the at least one nonvolatile memory cell.

2. The method of claim 1 , wherein in use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias.

3. The method of claim 2 , wherein the nonvolatile memory cell consists essentially of the diode and the first and the second electrodes electrically contacting the diode.

4. The method of claim 2 , wherein:

the nonvolatile memory cell consists essentially of the first and the second electrodes,

the diode and an antifuse; and

the diode and the antifuse are located in series between the first and the second electrodes.

5. The method of claim 1 , wherein the portion of the diode is doped with carbon in a concentration of greater than 1×10 20 cm −3 .

6. The method of claim 1 , wherein the portion of the diode is doped with nitrogen in a concentration of greater than 1×10 20 cm −3 .

7. The method of claim 1 , wherein the portion of the diode is doped with carbon and nitrogen in a concentration of greater than 1×20 20 cm −3 .

8. The method of claim 1 , wherein the diode comprises a p-i-n diode and at least an intrinsic region of the diode is doped with the at least one of carbon or nitrogen.

9. The method of claim 8 , wherein the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape.

10. The method of claim 1 , wherein the step of intentionally doping comprises ion implanting the at least one of carbon or nitrogen into the portion of the diode.

11. The method of claim 10 , wherein:

the diode is a p-i-n diode; and

the least one of nitrogen or carbon is implanted into the intrinsic region of the diode.

12. The method of claim 8 , wherein the step of doping comprises in-situ doping the diode with the at least one of carbon or nitrogen during diode layer deposition.

13. The method of claim 8 , wherein the step of doping comprises exposing the diode to at least one of a carbon or nitrogen containing plasma during or after diode layer deposition.

14. The method of claim 1 , further comprising applying a forward bias to the diode to switch the diode from the first resistivity, unprogrammed state to the second resistivity, programmed state, wherein the second resistivity state is lower than the first resistivity state.

15. The method of claim 14 , further comprising:

applying a reverse bias to the diode to switch the diode to a third resistivity, reset state, wherein the third resistivity state is higher than the second resistivity state; and

applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed set state, wherein the fourth resistivity state is lower than the third resistivity state.

16. The method of claim 1 , wherein the step of intentionally doping at least a portion of the diode comprises exposing the portion of the diode to a plasma of gas containing at least one of methane or ammonia.

17. A method of operating a nonvolatile memory device, comprising:

providing at least one memory cell which comprises a silicon, germanium or silicon-germanium diode, at least a portion of the diode being doped with at least one of carbon or nitrogen in a concentration greater than 1×10 20 cm −3 , wherein the concentration of carbon in the diode is lower than 1×10 21 cm −3 and the concentration of nitrogen in the diode is lower than 1×10 21 cm −3 , and wherein the diode has been switched from a first higher resistivity, unprogrammed state to a second lower resistivity, programmed state; and

applying a reverse bias to the diode to switch the diode to a third resistivity, reset state, wherein the third resistivity state is higher than the second resistivity state, and wherein the diode has a leakage current of less than 4×10 −10 A at −5.5V in the high resistivity, reset state.

18. The method of claim 17 , further comprising applying a forward bias to the diode to switch the diode to a fourth resistivity, programmed set state, wherein the fourth resistivity state is lower than the third resistivity state.

19. The method of claim 17 , further comprising sensing a resistivity state of the diode as a data state of the memory cell.

20. A method of operating a nonvolatile memory device, comprising:

providing at least one memory cell which comprises a silicon, germanium or silicon-germanium diode, at least an intrinsic region and at least one of a p-type and a n-type region being doped with at least one of carbon or nitrogen, wherein a concentration of carbon in the diode is lower than 1×10 21 cm −3 and a concentration of nitrogen in the diode is lower than 1×10 21 cm 31 3 , and wherein the diode has been switched from a first higher resistivity, unprogrammed state to a second lower resistivity, programmed state; and

applying a reverse bias to the diode to switch the diode to a third resistivity, reset state, wherein the third resistivity state is higher than the second resistivity state

wherein the diode has a leakage current of less than 4×10 −10 A at −5.5V in the high resistivity, reset state.

21. The method of claim 17 , wherein the diode comprises a polycrystalline silicon, germanium or silicon-germanium p-i-n pillar diode having a substantially cylindrical shape and the carbon or nitrogen provide at least one of reduced power, increased bandwidth or improved temperature characteristics to the memory cell during read and program operations.