Method of making a vertical phase change memory (PCM) and a PCM device
View Patent ↗A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
1. A method of making a phase change random access memory (PCM) device comprising:
forming active circuitry;
forming an insulating layer over the active circuitry;
forming a conductive layer in a top portion of the insulating layer;
forming a PCM stack on the conductive layer, wherein forming the PCM stack includes:
forming at least a heater layer,
forming a layer of phase change material overlying the heater layer, and
forming a top electrode layer overlying the layer of phase change material,
forming a top protection layer overlying the PCM stack;
patterning the top protection layer to form a patterned top protection layer and patterning a first portion of the PCM stack, wherein the first portion of the PCM stack excludes the heater layer;
forming a sidewall protection feature along a sidewall of the patterned top protection layer and first portion of the PCM stack, wherein the sidewall protection feature is in direct contact with the layer of phase change material, top electrode layer and the top protection layer, and wherein the sidewall spacer protection feature comprises a dielectric sidewall spacer; and
etching the heater layer using (i) the sidewall protection feature and (ii) the patterned top protection layer and the first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCM stack and thereby forming a completed memory bit of the PCM device,
wherein the top protection layer and the sidewall protection feature prevent any undesired back sputtering of the heater layer during the heater layer etch from creating an electrical short between the heater layer and the top electrode layer;
forming an interlevel dielectric layer (ILD) overlying the completed memory bit after the step of removing portions of the heater layer;
planarizing the ILD down to the top protection layer which acts as a planarization etch stop layer via chemical mechanical polishing and exposing the patterned top protection layer;
forming a contact opening by removal of the exposed patterned top protection layer; and
forming a contact metallization within the contact opening which is electrically coupled to the active circuitry by copper plating and subsequent chemical mechanical polishing (CMP).
2. The method of claim 1 , wherein the heater layer comprises one of a group consisting of TiN, TaN, TaSiN, W, and TiAlN.
3. The method of claim 1 , wherein the heater layer comprises a highly resistive metal, wherein the highly resistive metal has a resistivity of at least one milli-ohm-cm.
4. The method of claim 3 , wherein the top electrode layer also comprises a highly resistive metal, wherein an average resistivity of the top electrode layer and the heater layer has a resistivity of at least 1 milli-ohm-cm.
5. The method of claim 1 , wherein the phase change material comprises two of a group consisting of Ga, Ge, Sb, Se, S, and Te.
6. The method of claim 5 , further wherein the phase change material comprises Ge doped GaSb.
7. The method of claim 1 , wherein the top protection layer comprises a nitride anti-reflective coating (ARC).
8. The method of claim 1 , wherein patterning includes performing an etch of the top protection layer and the first portion of the PCM stack and landing either (i) on the heater layer or (ii) in the heater layer.
9. The method of claim 1 , wherein the dielectric sidewall spacer comprises one of a group consisting of an oxide and a nitride.
10. The method of claim 1 , wherein a bottom portion of the sidewall protection feature overlies a corresponding portion of the heater layer.
11. The method of claim 1 , further comprising:
forming an interlevel dielectric layer (ILD) after the step of etching the heater layer;
forming a contact opening in the ILD, wherein forming the contact opening in the ILD further includes removing the patterned top protection layer; and
forming a top metallization contact within the contact opening.
12. The method of claim 1 , further comprising:
forming an interlevel dielectric layer (ILD) after the step of etching the heater layer;
planarizing the ILD down to the top protection layer which acts as a planarization etch stop layer via chemical mechanical polishing and exposing the patterned top protection layer;
forming a contact opening by removal of the exposed patterned top protection layer; and
forming a contact metallization within the contact opening.
13. The method of claim 1 , still further comprising:
forming an interlevel dielectric layer (ILD) overlying the completed memory bit after the step of removing portions of the heater layer;
forming a contact opening in the ILD, wherein forming the contact opening in the ILD further includes removing the patterned top protection layer; and
forming a top metallization contact within the contact opening.