Fabricating ESD devices using MOSFET and LDMOS
View Patent ↗A method, including; simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate; and simultaneously forming a third doped region of the electrostatic discharge protection device and a fourth doped region of a first low power device by performing a second ion implantation into the semiconductor substrate, the first ion implantation different from the second ion implantation, the electrostatic discharge device being a different device type from the high-power device and the electrostatic discharge device having a different structure from the high-power device.
1. A method, comprising;
simultaneously forming a first doped region of an electrostatic discharge protection device and a second doped region of a high-power device by performing a first ion implantation into a semiconductor substrate;
simultaneously forming a third doped region of said electrostatic discharge protection device and a fourth doped region of a first low-power device by performing a second ion implantation into said semiconductor substrate, said first ion implantation different from said second ion implantation, said electrostatic discharge device being a different device type from said high-power device and said electrostatic discharge device having a different structure from said high-power device;
simultaneously forming a fifth doped region of said electrostatic discharge protection device and a sixth doped region of a second low-power device by performing a third ion implantation into said semiconductor substrate, said third ion implantation different from said first, and second ion implantations;
said first low-power device is a CMOS logic PFET, said second low-power device is a CMOS logic NFET, said high-power device is a lateral double diffused field effect transistor, and said electrostatic protection device is a shunt transistor; and
said first doped region is a P-well of said shunt transistor, said second doped region is a P-well of said lateral double diffused field effect transistor, said third doped region is a P-body contact of said shunt transistor, said fourth doped region is a source/drain of said CMOS logic PFET, said fifth doped region is a source/drain of said shunt transistor, and said sixth doped region is a source/drain of said CMOS logic NFET.
2. The method of claim 1 , wherein all ion implantations used to form said electrostatic protection device are ion implantations selected from the group of ion implantations consisting of ion implantations used to form doped regions of CMOS logic PFETs and NFETs in said semiconductor substrate and ion implantations used to form doped regions of said high-power device in said semiconductor substrate.
3. The method of claim 1 , wherein three ion implantations are used to form respective doped regions of said electrostatic protection device are the same ion implantations used to form respective doped regions of CMOS logic PFETs and NFETs and at least additional one ion implantation used to form an additional doped region of said electrostatic protection device is a same ion implantation used to form a doped region of said high-power device.
4. The method of claim 1 , further including:
forming dielectric trench isolations in said semiconductor substrate, said dielectric trench isolation abutting said low-power device, said high-power device and said electrostatic discharge protection device.
5. The method of claim 1 , further including:
connecting said low-power device, said high-power device and said electrostatic discharge protection device into an integrated circuit.
6. The method of claim 1 , wherein said first ion implantation is selected from the group consisting of P-type source/drain ion implantations, N-type source/drain ion implantations, P-well ion implantations and N-well ion implantations used to fabricate CMOS logic field effect transistors and said second ion implantation is selected from the group consisting of N-body ion implantations, P-body ion implantations, N-tub ion implantations and second N-type source ion-implantations, one or more of which are used to fabricate lateral double diffused field effect transistors, said P-type source/drain ion implantations, N-type source/drain ion implantations, P-well ion implantations, N-well ion implantations, N-body ion implantations, P-body ion implantations, N-tub ion implantations and second N-type source ion-implantations being different ion implantations.
7. The method of claim 6 , wherein the ion implantations in order of decreasing ion implantation dose are said N-type source/drain and said P-type source/drain ion implantations, said second N-type source ion-implantation, said N-well and said P-well ion implantations, said N-body and P-body ion implantations, and said N-tub ion implantation.
8. The method of claim 6 , wherein the ion implantations in order of increasing ion implantation energy are said P-type and N-type source/drain ion implantation, said second N-type source ion-implantation, said N-well and said P-well ion implantations, said N-body and P-body ion implantations, and said N-tub ion implantation.
9. The method of claim 1 , wherein said first ion implant also forms a P-well of said CMOS logic NFET and said second ion implantation also forms a P-body contact of said shunt transistor.
10. The method of claim 1 , wherein said P-body contact of said shunt transistor is isolated from said source/drain of said shunt transistor by dielectric trench isolation.
11. The method of claim 1 , wherein said P-body contact of said shunt transistor is isolated from said source/drain of said shunt transistor by a region of locally oxidized silicon (LOCOS).