Selective etch chemistries for forming high aspect ratio features and associated structures
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as Si x M y H z , where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x≧1, y≧0 and z≧0. The carbon species can be generated from a carbon compound, such as C α M β H γ , where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and α≧1, β≧0 and γ≧0. The oxygen species can be generated from an oxygen compound, such as O 2 , which can react with carbon to form a volatile compound.
1. A method for integrated circuit fabrication, comprising:
providing an interlevel dielectric (ILD) layer overlying a substrate;
providing a masking layer overlying the ILD layer, the masking layer having an opening exposing the ILD layer;
forming a hole in the ILD layer by etching into the opening, wherein forming the hole comprises:
initially etching exposed parts of the ILD layer with plasma-excited species generated from a carbon compound without contacting the exposed parts to plasma-excited silicon species; and
subsequently etching exposed parts of the ILD layer with both plasma-excited species generated from a silicon compound and plasma-excited species generated from the carbon compound.
2. The method of claim 1 , wherein contacting the exposed parts of the ILD layer forms a passivating layer on at least parts of sidewalls of the opening.
3. The method of claim 1 , wherein the silicon compound has the formula Si x M y H z , wherein Si is silicon, H is hydrogen and M is one or more halogens selected from the group consisting of fluorine (F), bromine (Br), chlorine (Cl) and iodine (I), and wherein x≧1, y≧0 and z≧0.
4. The method of claim 3 , wherein the silicon compound has the formula Si x M y H z , wherein x≧1, y≧1 and z≧0.
5. The method of claim 1 , wherein the carbon compound has the formula C α M β H γ , wherein C is carbon, H is hydrogen and M is one or more halogens selected from the group consisting of fluorine (F), bromine (Br), chlorine (Cl) and iodine (I), and wherein α≧1, β≧0 and γ≧0.
6. The method of claim 5 , wherein the carbon compound has the formula C α M β H γ , wherein α≧1, β≧1 and γ≧0.
7. The method of claim 1 , wherein initially contacting exposed parts of the ILD layer and subsequently contacting exposed parts of the ILD layer comprise contacting the ILD layer with plasma excited species generated from an oxygen compound.
8. A method for semiconductor processing, comprising:
providing a silicon-containing dielectric layer; and
etching openings in the dielectric layer, wherein etching the openings in the dielectric layer comprises:
initially etching exposed surfaces of the dielectric layer with plasma-excited species generated from a carbon compound; and
subsequently increasing a depth of the openings while contacting exposed surfaces of the openings to plasma-excited species generated from a silicon compound,
wherein initially etching exposed surfaces of the dielectric layer is performed without contacting the exposed surface with the plasma-excited species generated from the silicon compound.
9. The method of claim 8 , wherein subsequently increasing the depth of the openings comprises contacting the exposed surfaces of the openings with plasma-excited species generated from the carbon compound.
10. The method of claim 8 , wherein initially etching exposed surfaces and subsequently increasing the depth of the openings further comprises contacting the dielectric layer with a plasma-excited oxygen species.
11. The method of claim 8 , wherein subsequently increasing the depth of the openings comprises intermittently exposing the exposed portions to plasma-excited species generated from the silicon compound.
12. The method of claim 8 , wherein the silicon-containing dielectric comprises silicon oxide.
13. The method of claim 12 , further comprising a masking layer overlying the dielectric layer, the masking layer having holes through which the openings in the dielectric layer are etched, wherein the masking layer is formed of a carbon material.
14. The method of claim 13 , wherein the carbon material is a photoresist.
15. The method of claim 13 , wherein the carbon material is amorphous carbon.
16. The method of claim 13 , wherein a ratio of the etch rate for the dielectric layer and an etch rate for the masking layer, during initially etching, is greater than or equal to about 4:1.
17. The method of claim 8 , wherein exposed portions of the dielectric layer are exposed by openings in a mask layer overlying the dielectric layer.
18. The method of claim 8 , wherein etching openings in the dielectric layer forms openings with depth-to-width ratios greater than or equal to about 30:1.
19. The method of claim 8 , wherein etching the dielectric layer comprises forming trenches.
20. The method of claim 8 , wherein etching the openings in the dielectric layer forms openings having widths with a variation of less than about 10 nm RMS, within 3 sigma.