Method of forming pixel cell having a grated interface

1. A method of forming a pixel cell, the method comprising the acts of:

forming a plurality of trenches within a silicon substrate dedicated for a first doped region of a photosensor, wherein the first doped region is over an area within the silicon substrate dedicated for a second doped region of the photosensor; and

providing an oxide layer within and over the plurality of trenches to form a grated interface between the oxide layer and the plurality of trenches formed within the silicon substrate dedicated for the first doped region of the photosensor, wherein the oxide layer completely fills the plurality of trenches such that the topmost surface of the oxide layer is substantially planar.

2. The method of claim 1 , further comprising the act of forming a photosensor comprising the first doped region and the second doped region within the silicon substrate.

3. The method of claim 2 , wherein the act of forming a photosensor comprises the act of doping the silicon substrate dedicated for the first doped region with either a p-type or n-type dopant and doping the silicon substrate dedicated for the second doped region with the dopant type not used to dope the silicon substrate for the first doped region.

4. The method of claim 3 , wherein the act of doping results in a pinned photodiode.

5. The method of claim 1 , wherein the plurality of trenches is formed by a method selected from the group consisting of etching the silicon substrate, reactive etching the silicon substrate, and chemical etching the silicon substrate.

6. The method of claim 1 , wherein the plurality of trenches within the silicon substrate dedicated for the first doped region of the photosensor is formed by providing a photoresist pattern over the silicon substrate, and forming a plurality of silicon columns by epitaxial growth.

7. The method of claim 1 , wherein the plurality of trenches within the silicon substrate dedicated for the first doped region of the photosensor is formed having a substantially semi-rectangular shape.

8. The method of claim 1 , wherein at least one of the plurality of trenches within the silicon substrate dedicated for the first doped region of the photosensor is formed to have a predetermined depth within a range from about 10 nm to about 250 nm, and the grated interface has a predetermined period within a range from about 100 nm to about 1000 nm.

9. The method of claim 1 , wherein at least one of the plurality of trenches within the silicon substrate dedicated for the first doped region of the photosensor is formed to have at least three distinct sidewall regions having at least three distinct depths to define a grated interface between the oxide layer and the substrate.

10. The method of claim 1 further comprising forming a layer over the oxide layer, the layer selected from the group consisting of a metallization layer and an insulating layer.

11. A method of forming a pixel cell, the method comprising:

forming a photosensor comprising a first doped region and a second doped region on a silicon substrate;

forming a storage node provided on the silicon substrate;

forming a transfer transistor having a gate structure provided on the silicon substrate operable for electrically interconnecting the photosensor and storage node;

forming a plurality of trenches within only the first doped region of the silicon substrate over an area dedicated for light to pass to the photosensor;

providing an oxide layer within and over the plurality of trenches to form a grated interface between the oxide layer and the plurality of trenches, wherein the oxide layer has a first surface in contact with the trenches and a second surface opposite the first surface, the oxide layer filling the plurality of trenches such that the entire second surface of the oxide layer is substantially planar; and

forming a material layer over the oxide layer.

12. The method of claim 11 wherein the material layer is formed from tetraethyl orthosilicate.

13. The method of claim 12 further comprising depositing a boro-phospho-silicate glass layer over the material layer.

14. A method of forming a pixel cell, the method comprising:

forming a photosensor comprising a first doped region and a second doped region provided on a silicon substrate;

forming a storage node provided on the silicon substrate;

forming a transfer transistor having a gate structure provided on the silicon substrate operable for electrically interconnecting the photosensor and storage node;

forming a first plurality of trenches within the first doped region of the silicon substrate over an area dedicated for light to pass to the photosensor;

providing an oxide layer within the first plurality of trenches to form a first grated interface;

forming a second plurality of trenches within the topmost surface of the oxide layer; and

providing a material layer within and over the second plurality of trenches to form a second grated interface, wherein the material layer totally fills the second plurality of trenches and the topmost surface of the material layer is substantially planar.

15. The method of claim 14 , wherein at least one of the first plurality of trenches within the first doped region of the silicon substrate, and the second plurality of trenches within the topmost surface of the oxide layer, is formed to have a predetermined depth within a range from about 10 nm to about 250 nm.

16. The method of claim 14 , wherein at least two of the first plurality of trenches within the first doped region of the silicon substrate, and the second plurality of trenches within the topmost surface of the oxide layer, has a predetermined period within a range from about 100 nm to about 1000 nm.

17. The method of claim 14 wherein at least one of the first plurality of trenches within the first doped region of the silicon substrate is formed to have at least three distinct sidewall regions having at least three distinct depths to define a grated interface within the first grated interface.

18. A method of forming an integrated circuit comprising:

forming an array of pixel cells for capturing an image, the method of forming at least one pixel cell of the array comprising:

forming a silicon substrate having a photosensor comprising a first doped region over a second doped region, and forming a plurality of trenches exclusively within the first doped region of the photosensor located over the second doped region of the photosensor, wherein a distance measured from the beginning of at least one trench to the beginning of an adjacent trench is about 340 nm, and the at least one trench has a depth of about 100 nm; and

foaming an oxide layer provided within and over the plurality of trenches within the first doped region, wherein the oxide layer entirely fills the trenches such that the topmost surface of the oxide layer is substantially planar.

19. The method of claim 18 , wherein at least one trench has at least three distinct sidewall regions having at least three distinct depths to define a grated interface.

20. The method of claim 18 , wherein at least one trench has a substantially semi-rectangular shape.

21. A method for forming an integrated circuit, comprising:

forming an array of pixel cells, at least one pixel cell of the array formed by a method comprising:

forming a charge generating region comprising a first doped region and a second doped region by a method comprising:

forming a first plurality of trenches at an upper portion of the charge generating region comprising the first doped region,

forming a first material layer within and over the topmost surface of the first plurality of trenches wherein the material layer completely fills the trenches such that the topmost surface of the material layer is substantially planar and creates a hybrid interface capable of preventing reflection of incident light striking the interface, and

forming a second material layer within and over the first material layer;

forming a first charge collection region;

forming a second charge collection region for receiving charge from the first charge collection region; and

forming a gate for electrically coupling the first and second charge collection regions, the gate being formed over the semiconductor substrate.

22. The method for forming an integrated circuit of claim 21 , wherein the first plurality of trenches has a period of about 340 nm and a depth of about 100 nm.

23. The method for forming an integrated circuit of claim 21 , wherein the first plurality of trenches has a predetermined period and a predetermined depth for each wavelength of incident light.

24. A method of forming a pixel array comprising:

forming a plurality of photodiodes for receiving incident light from a scene and for storing charges associated with the incident light, the plurality of photodiodes providing stored charges representing an image of the scene, the method of forming each photodiode comprising;

forming a first conductivity type region provided at an upper surface of a semiconductor substrate, and

forming a second conductivity type region within the semiconductor substrate below the first conductivity type region, the second conductivity type region for storing the charges;

forming a plurality of grated interfaces respectively associated with the photodiodes through which the incident light passes, the method for forming each of the grated interfaces comprising;

forming a plurality of trenches in the first conductivity type region of a respective photodiode; and

providing a material having an index of refraction different than that of the semiconductor substrate over an upper surface of the first conductivity type region, the material having a first surface in contact with the trenches and a second surface opposite the first surface, the material filling the trenches such that the entire second surface is substantially planar, the material and semiconductor substrate providing an index of refraction for each grating that is lower than the index of refraction of the semiconductor substrate and higher than the index of refraction of the material.

25. The method of claim 24 wherein the first conductivity type region is p-type and the second conductivity type region is n-type and the semiconductor substrate is p-type.

26. The method of claim 24 wherein the first conductivity type region is n-type and the second conductivity type region is p-type and the semiconductor substrate is n-type.

27. The method of claim 24 wherein the plurality of trenches in the first conductivity region of a respective photodiode are formed by etching.

28. The method of claim 24 wherein the plurality of trenches in the first conductivity region of a respective photodiode are formed by forming a plurality of columns by epitaxial growth.

29. The method of claim 24 wherein the plurality of trenches in the first conductivity region of a respective photodiode are formed having a substantially semi-rectangular shape.

30. The method of claim 24 wherein at least one of the plurality of trenches in the first conductivity region of a respective photodiode is formed to have a predetermined depth within a range from about 10 nm to about 250 nm, and the grated interface has a predetermined period within a range from about 100 nm to about 1000 nm.

31. The method of claim 24 wherein the plurality of trenches in the first conductivity region of a respective photodiode are formed to have a plurality of different depths.

32. The method of claim 24 further comprising forming a layer over the material layer, the layer selected from the group consisting of a metallization layer and an insulating layer.

33. The method of claim 24 further comprising forming an insulating layer over the material layer, the insulating layer comprising tetraethyl orthosilicate.

34. The method of claim 33 further comprising depositing a boro-phospho-silicate glass layer over the insulating layer.