Method and system for switching between two (or more) reference signals for clock synchronization
An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R 0 (for the newly selected reference clock signals) retains its last value prior to the switch, and another register R 1 stores subsequent signal timing differences between the timing signal and the newly selected reference clock signals. To synchronize the timing signal with the new reference clock signal without distorting the timing signal and impairing the operation of the computation system, differences between R 1 and R 0 are output (for successive time intervals) for iteratively adjusting the timing signals. The contents of the offset register R 0 is incrementally changed toward a predetermined value (i.e., zero) thereby gradually adjusting the timing signals to factor in a potentially large timing change when switching between reference clock signals.
1. A clock synchronization device for phase aligning timing signals for a computational system to one of a plurality of reference clock signals, comprising:
a clock selector for selecting between at least a first of the plurality of reference clock signals and an alternative of the plurality of reference clock signals for phase aligning the timing signals therewith;
a phase locked loop for receiving the first reference clock signals, and the alternative reference clock signals;
wherein the phase locked loop includes:
(a) one or more phase error registers, wherein:
(i) when the first reference clock signals are selected for phase aligning the timing signals, one of the one or more phase error registers repeatedly receives and stores data indicative of phase errors between the timing signals, and the first reference clock signals, and
(ii) when the alternative reference clock signals are selected for phase aligning the timing signals, one of the one or more phase error registers repeatedly receives and stores data indicative of phase errors between the timing signals, and the alternative reference clock signals;
(b) a first phase offset register corresponding to the first reference clock signals, wherein the first phase offset register repeatedly receives and stores data indicative of a phase error between the timing signals and the first reference clock signals, when the first reference clock signals are not selected by the clock selector for phase aligning the timing signals;
(c) a second phase offset register corresponding to the alternative reference clock signals, wherein the second phase offset register repeatedly receives and stores data indicative of a phase error between the timing signals and the alternative reference clock signals, when the alternative reference clock signals are not selected by the clock selector for phase aligning the timing signals;
wherein when the clock selector signals a switch from one of the first and alternative reference clock signals to the other of the first and alternative reference clock signals, the data in the one of the first and second phase offset registers corresponding to the other reference clock signals is:
(d) combined with one of the phase error registers having data indicative of phase errors between the timing signals and the other reference clock signals for obtaining a phase error for correction, and
(e) modified so that a subsequent combining with the one of the phase error registers having data indicative of phase errors between the timing signals and the other reference clock signals brings the timing signals into closer phase alignment with the other reference clock signals.
2. The clock synchronization device of claim 1 , wherein the data in the corresponding one of the first and second phase offset registers is repeatedly combined with the one of the phase error registers, and modified so that a subsequent combining with the one of the phase error registers, and the other reference clock signals brings the timing signals into closer phase alignment with the other reference clock signals.
3. The clock synchronization device of claim 1 , wherein the phase locked loop includes a numerically controlled oscillator.
4. A method for adjusting timing signals for a computational system with various ones of a plurality of reference clock signals, comprising:
selecting one of the plurality of reference clock signals for adjusting the timing signals into being consistent with a timing characteristic of the selected reference clock signals;
providing, for an alternative one of the plurality of reference clock signals that is different from the selected reference clock signals, a corresponding data register (R 1 ) for storing data indicative of the difference between the timing signals and the alternative reference clock signals;
receiving a signal for selecting the alternative reference clock signals for adjusting the timing signals;
for a signal detector receiving the alternative reference clock signals, a step of outputting a difference (D 1 ) between the timing signals and the alternative reference clock signals, at a time T 1 , to a register (R 2 ) different from the register R 1 ;
storing the difference D 1 as a value of the register R 2 ;
determining a difference between the R 1 and R 2 for adjusting the timing signals;
changing a value of the data register R 1 so that for a difference (D 2 ) between the timing signals and the alternative reference clock signals, at a time T 2 , in the register R 2 , a subsequent difference between the R 1 and R 2 is used for adjusting the timing signals into being more consistent with a timing characteristic of the alternative reference clock signals.
5. The method of claim 4 , wherein the timing characteristic of at least one of the selected reference clock signals, and the alternative reference clock signals includes a signal phase.
6. The method of claim 4 , further including a step of iteratively changing the value of the data register R 1 so that the value becomes closer or equal to a predetermined value.
7. The method of claim 4 , further including outputting the subsequent difference to a low pass filter.