Method for manufacturing twin bit structure cell with Al
View Patent ↗A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure.
1. A method for forming a non-volatile memory structure, the method comprising:
providing a semiconductor substrate including a surface region;
forming a gate dielectric layer overlying the surface region;
forming a polysilicon gate structure overlying the gate dielectric layer;
forming an undercut region underneath the polysilicon gate structure in a portion of the gate dielectric layer;
subjecting the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying a periphery of the polysilicon gate structure;
forming an aluminum oxide material overlying the polysilicon gate structure filling the undercut region, the aluminum oxide material being formed by depositing a first aluminum oxide layer overlying the first silicon oxide layer, depositing a nanocrystalline silicon material overlying the first aluminum oxide layer and depositing a second aluminum oxide layer overlying the nanocrystalline silicon material;
subjecting the aluminum oxide material to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region; and
forming a sidewall spacer structure overlying a side region of the polysilicon gate structure.
2. The method of claim 1 further comprising forming a source region and a drain region.
3. The method of claim 1 wherein the sidewall spacer structure is formed by depositing a conformal dielectric layer overlying the polysilicon gate structure followed by a selective etching process.
4. The method of claim 1 wherein the semiconductor substrate is a P-type silicon wafer.
5. The method of claim 1 wherein the undercut region is formed using a self-limiting etching process.
6. The method of claim 1 wherein the undercut region is a void region.
7. The method of claim 1 wherein the nanocrystalline silicon has an outer surface, the outer surface being capable of accumulating electrical charge.
8. The method of claim 1 wherein the aluminum oxide material is a high k dielectric material.
9. The method of claim 1 wherein the first aluminum oxide layer and the second aluminum oxide layer are formed using atomic layer deposition.
10. The method of claim 9 wherein the first aluminum oxide layer and the second aluminum oxide layer each has an aluminum to oxygen ratio of about 1:1.3 to about 1:1.7.
11. The method of claim 1 wherein the insert region provides a double-sided bit structure.
12. The method of claim 1 wherein the nanocrystalline silicon material has a thickness ranging from about 2 nm to about 4 nm.
13. The method of claim 1 wherein the aluminum oxide material is characterized by a first thickness, the first thickness being controlled by a thickness of the gate dielectric layer.
14. The method of claim 1 further comprises forming active regions in a vicinity of the surface region of the semiconductor substrate.
15. The method of claim 14 wherein the active regions are formed by an implantation process using an N type arsenic as an impurity species and the polysilicon gate structure, including the sidewall spacer structure as a mask.
16. The method of claim 1 wherein the selective etching process comprises a reactive ion etching process.
17. The method of claim 1 further comprising forming a void region adjacent to the aluminum oxide material in the insert region.