Methods of forming memory cells on pillars and memories with memory cells on pillars

1. A method for fabricating a memory array, comprising:

fabricating first and second successively adjacent rows of memory cells on a first row of pillars, each pillar of the first row of pillars having one memory cell of the first row of memory cells and one memory cell of the second row of memory cells on opposite sides thereof;

fabricating third and fourth successively adjacent rows of memory cells on a second row of pillars successively adjacent to the first row of pillars, each pillar of the second row of pillars having one memory cell of the third row of memory cells and one memory cell of the fourth row of memory cells on opposites side thereof, wherein the second and third rows of memory cells are successively adjacent to each other;

fabricating a control gate between the first and second rows of pillars, the control gate to control the memory cells of the second and third rows of memory cells;

fabricating a word line coupled to the control gate so that all of the memory cells of the second row of memory cells are coupled to one side of the word line and all of the memory cells of the third row of memory cells are coupled to an opposite side of the word line; and

forming alternating first bit lines so that each of the memory cells of the second row of memory cells is coupled to a respective one of the alternating first bit lines and forming alternating second bit lines so that each of the memory cells of the third row of memory cells is coupled to a respective one of the alternating second bit lines;

wherein the alternating first bit lines are different from the alternating second bit lines; and

wherein an alternating second bit line is between a pair of alternating first bit lines and is successively adjacent to the alternating first bit lines of the pair of alternating first bit lines.

2. The method of claim 1 , further comprising:

forming a dielectric layer over the pillars of each of the first and second rows of pillars; and

forming a metal contact over each pillar of the first and second rows of pillars and through the dielectric layer over that pillar.

3. The method of claim 2 , wherein a metal contact formed over a respective pillar is coupled to a drain region formed on that pillar and wherein control gates of the memory cells fabricated on opposite sides of a pillar are fabricated on channel regions located on the opposite sides of that pillar and between source regions formed on the opposite sides of that pillar and the drain region, and further comprising forming the alternating first bit lines over the dielectric layer over the pillars of the first row of pillars and coupled to the contacts over the pillars of the first row of pillars and forming the alternating second bit lines over the dielectric layer over the pillars of the second row of pillars and coupled to the contacts over pillars of the second row of pillars.

4. The method of claim 3 , wherein fabricating rows of memory cells comprises fabricating floating gate layers vertically along each side of the pillars of each of the first and second rows of pillars.

5. The method of claim 4 , further comprising forming a tunnel insulator layer between each pillar and its respective floating gate layers and a gate insulator layer between each floating gate layer and its respective control gate.

6. The method of claim 1 , wherein the memory cells of the second row of memory cells are staggered with respect to the memory cells of the third row of memory cells.

7. A method of fabricating at least three pairs of floating gate transistors, comprising:

fabricating at least three pillars of substrate material;

fabricating each of the at least three pairs of floating gate transistors on respective ones of the at least three pillars, wherein each of the at least three pairs of floating gate transistors comprises first and second floating gate transistors, and wherein fabricating a respective pair of the at least three pairs of floating gate transistors on a respective one of the at least three pillars comprises:

fabricating first and second source regions and a drain region, each source region spaced apart vertically from the drain region to define a channel of the first floating gate transistor of the respective pair of the at least three pairs of floating gate transistors between the first source region and the drain region and a channel of the second floating gate transistor of the respective pair of the at least three pairs of floating gate transistors between the second source region and the drain region;

fabricating a first layer of oxide over the channels of the first and second floating gate transistors of the respective pair of floating gate transistors;

fabricating substantially vertically configured floating gate structures of the first and second floating gate transistors of the respective pair of floating gate transistors over the first layer of oxide and respectively adjacent to the channels of the first and second floating gate transistors of the respective pair of floating gate transistors;

fabricating a second oxide layer over the floating gate structures; and

fabricating control gate structures of the first and second floating gate transistors of the respective pair of floating gate transistors over the second layer of oxide and respectively adjacent to the floating gate structures of the first and second floating gate transistors of the respective pair of floating gate transistors;

fabricating a word line commonly coupled to the control gate structures of the first floating gate transistors of first and second pairs of the at least three pairs of floating gate transistors and the second floating gate transistor of a third pair of the at least three pairs of floating gate transistors;

fabricating a first bit line coupled to the first floating gate transistor of the first pair of the at least three pairs of floating gate transistors;

fabricating a second bit line coupled to the first floating gate transistor of the second pair of the at least three pairs of floating gate transistor; and

fabricating a third bit line coupled to the second floating gate transistor of the third pair of the at least three pairs of floating gate transistors;

wherein the first floating gate transistors of first and second pairs of the at least three pairs of floating gate transistors are coupled to a same side of the word line and the second floating gate transistor of the third pair of the at least three pairs of floating gate transistors is coupled to an opposite side of the word line; and

wherein the third bit line is between the first and second bit lines, the third bit line is successively adjacent to the first bit line, and the second bit line is successively adjacent to the third bit line.

8. The method of claim 7 , further comprising forming a dielectric layer over each pillar.

9. The method of claim 8 , further comprising forming a metal contact through the dielectric layer to the drain region of each pillar.

10. The method of claim 7 , wherein fabricating the at least three pillars comprises pattern etching the substrate using a nitride mask.

11. The method of claim 7 , wherein fabricating the control gate structures of the first and second floating gate transistors of the respective pair of floating gate transistors comprises a chemical-mechanical planarization.

12. The method of claim 7 , wherein the control gate structures of the first and second floating gate transistors of the respective pair of floating gate transistors are polysilicon.

13. The method of claim 7 , wherein the word line is formed from a self-aligned silicide layer.

14. The method of claim 7 , wherein the control gate structures of the first and second floating gate transistors of the respective pair of floating gate transistors are not contiguous.

15. The method of claim 7 , wherein the source regions are located on opposite sides of the respective pillar and the drain region is formed in an upper surface of the respective pillar.

16. A method for fabricating a memory array, the method comprising:

forming a plurality of pillars in a semiconductor arranged in row and column fashion, each column of pillars formed in a staggered pattern from adjacent columns of pillars;

forming a pair of memory cells on each pillar, wherein forming a pair of memory cells on a respective pillar comprises:

forming a drain region substantially vertically separated from each of a first and a second source region in the semiconductor to define respective first and second channel regions in the respective pillar, the first and second source regions separated by the respective pillar;

forming a tunnel insulator over each channel region;

forming a floating gate structure in a substantially vertical orientation adjacent to each channel region and over each respective tunnel insulator;

forming a gate insulator layer over each floating gate structure; and

forming a control gate structure over each gate insulator layer in a substantially vertical orientation adjacent to a respective floating gate structure;

forming an isolation region between each pair of adjacent control gate structures;

forming word lines coupled to the control gate structures; and

forming bit lines over the word lines;

wherein memory cells coupled to a first side of a word line are within one row of memory cells and memory cells coupled to a second side of the word line are within an adjacent row of memory cells, wherein the second side of the word line is opposite the first side of the word line;

wherein the memory cells of the one row of memory cells are coupled to alternating bit lines and the memory cells of the adjacent row of memory cells are coupled to alternating bit lines;

wherein the alternating bit lines coupled to the memory cells of the one row of memory cells are different from the alternating bit lines coupled to the memory cells of the adjacent row of memory cells; and

wherein an alternating bit line that is coupled to one of memory cells of the adjacent row of memory cells is between a pair of alternating bit lines coupled to a pair of successively adjacent memory cells of the one row of memory cells and is successively adjacent to the bit lines of the pair of alternating bit lines coupled to the pair of successively adjacent memory cells of the one row of memory cells.

17. The method of claim 16 , wherein forming the plurality of pillars comprises pattern etching the substrate using a nitride mask.

18. The method of claim 16 , further comprising forming a dielectric layer over the plurality of pillars.

19. The method of claim 18 , further comprising forming a contact through the dielectric layer coupled to a drain region and a bit line such that the drain region in each pillar is coupled to adjacent pillars by the bit line.

20. The method of claim 16 , wherein fabricating the control gate structures comprises a chemical-mechanical planarization.

21. A method for fabricating a memory array, comprising:

forming rows of memory cells on pillars separated by isolation regions therebetween, each pillar having a pair of memory cells, each on an opposite side thereof;

forming control gates substantially between the rows of memory cells;

forming word lines for the array coupled to the control gates;

forming bit lines over the word lines; and

wherein every memory cell coupled to a first side of a word line is within one row of memory cells and every memory cell coupled to a second side of the word line that is opposite the first side of the word line is within an adjacent row of memory cells;

wherein the memory cells of the one row of memory cells are coupled to alternating bit lines and the memory cells of the adjacent row of memory cells are coupled to alternating bit lines;

wherein the alternating bit lines coupled to the memory cells of the one row of memory cells are different from the alternating bit lines coupled to the memory cells of the adjacent row of memory cells; and

wherein an alternating bit line that is coupled to one of memory cells of the adjacent row of memory cells is between a pair of alternating bit lines coupled to a pair of successively adjacent memory cells of the one row of memory cells and is successively adjacent to the bit lines of the pair of alternating bit lines coupled to the pair of successively adjacent memory cells of the one row of memory cells.