IP Library Granted Patent US 8,143,153
Granted Patent B2
US 8,143,153 · App. 13/075,463 · Granted Mar 27, 2012

Method for manufacturing semiconductor device

Assignee: Fujitsu Semiconductor Limited
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Quick Facts
Patent No.
US 8,143,153
App. No.
13/075,463
Granted
Mar 27, 2012
Kind
B2
Abstract

A method of manufacturing a semiconductor device, including: forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO 2 film and including the multilayer interconnection structure; forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.

Claims (21)

1. A method of manufacturing a semiconductor device, comprising:

forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body formed of stacked layers of a plurality of interlayer insulating films lower in dielectric constant than a SiO 2 film and including the multilayer interconnection structure;

forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate;

forming a film including Si and C as principal components and covering sidewall surfaces and a bottom surface of the groove; and

forming a protection film on the film along the sidewall surfaces and the bottom surface of the groove.

2. A method of manufacturing a semiconductor device, comprising:

forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body including the multilayer interconnection structure;

forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate; and

forming a protection film covering sidewall surfaces and a bottom surface of the groove,

wherein the groove is formed using a metal pattern formed on the multilayer interconnection structure as a mask.

3. A method of manufacturing a semiconductor device, comprising:

forming a moisture resistant ring surrounding a multilayer interconnection structure in a layered body including the multilayer interconnection structure;

forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate;

forming a protection film covering a first sidewall surface, a bottom surface, and a second sidewall surface of the groove, the first sidewall surface being closer to the moisture resistant ring than the second sidewall surface is, the second sidewall surface being closer to the scribe line than the first sidewall surface is; and

at least partially removing a part of the protection film covering the second sidewall surface of the groove.

4. A method of manufacturing a semiconductor device, comprising:

forming a moisture resistant ring in a multilayer interconnection structure included in a layered body;

forming a groove in the layered body between the moisture resistant ring and a scribe line, the groove reaching a surface of a semiconductor substrate;

forming an insulating protection film covering sidewall surfaces and a bottom surface of the groove; and

removing the insulating protection film on an upper surface of the layered body on an outer side of the groove.

5. The method of manufacturing a semiconductor device as claimed in claim 4 , wherein said removing removes a first part of the insulating protection film on the upper surface of the layered body on the outer side of the groove with a second part of the insulating protection film covering the upper surface of the layered body on an inner side of the groove.

Assignments (1)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
Continuity (3)
Division 12564989 · Sep 23, 2009
Continuation PCTJP2007057156 · Mar 30, 2007
Related Publication 20110177672A1 · Jul 21, 2011