Semiconductor device with amorphous silicon monos memory cell structure and method for manufacturing thereof
View Patent ↗A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.
1. A device with amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure, the device comprising:
a substrate;
a dielectric layer on the substrate, the dielectric layer being associated with a first surface;
one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions being associated with a second surface and including an n-type a-Si layer, a diffusion barrier layer, and a conductive layer, the n-type a-Si layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the conductive layer, the second surface consisting of n-type a-Si and being substantially co-planar with the first surface;
an intrinsic (i-type) a-Si layer overlying the first surface and the second surface;
a p-type a-Si layer overlying the i-type a-Si layer;
an oxide-nitride-oxide (ONO) layer overlying the p-type a-Si layer; and
at least one control gate overlying the ONO layer.
2. The device of claim 1 wherein the dielectric layer comprises silicon oxide.
3. The device of claim 1 wherein the conductive layer is metal silicide comprising TiSi2.
4. The device of claim 3 wherein the metal silicide layer is capable of coupling with memory array bitlines electrically.
5. The device of claim 1 wherein the diffusion barrier layer is metal-nitride comprising TiN.
6. The device of claim 1 wherein the p-type a-Si layer overlying the i-type a-Si layer is capable of forming an amorphous silicon p-i-n diode junction at the second surface.
7. The device of claim 1 wherein the ONO layer comprises a silicon nitride layer for charge trapping, sandwiched by an upper silicon oxide block layer and a bottom silicon oxide tunnel layer.
8. The device of claim 1 wherein the control gate is characterized by a metal layer pattern overlying the ONO layer.
9. The device of claim 8 wherein the metal layer comprises titanium.
10. The device of claim 8 wherein the metal layer comprises aluminum.
11. The device of claim 8 wherein the metal layer couples with memory array wordlines electrically.
12. The device of claim 8 wherein the control gate is positioned over at least one source and one drain region.