Methods for forming three-dimensional memory devices, and related structures
Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example.
1. A method of forming a semiconductor device, comprising:
forming at least one memory array comprising a plurality of memory devices over another memory array comprising another plurality of memory devices such that a conductive material formed between a foundational material for the at least one memory array and a dielectric material overlying the another memory array electrically contacts an active region of at least one of the plurality of memory devices.
2. The method of claim 1 , wherein forming at least one memory array over another memory array comprises:
forming the another memory array;
forming the dielectric material over the another memory array;
forming the conductive material over at least a portion of the dielectric material;
forming the foundational material over at least the conductive material; and
forming the at least one memory array over the foundational material.
3. The method of claim 1 , wherein forming at least one memory array over another memory array comprises forming a NAND array over another NAND array.
4. The method of claim 2 , wherein forming the conductive material over at least a portion of the dielectric material comprises:
removing at least a portion of the dielectric material to form at least one opening extending partially through the at least a portion of the dielectric material; and
depositing the conductive material within the at least one opening.
5. The method of claim 4 , wherein forming the foundational material over at least the conductive material comprises forming the foundation material over each of the conductive material and the dielectric material.
6. The method of claim 5 , wherein forming the at least one memory array over a foundation material comprising a semiconductor material comprises forming the at least one memory array on a foundation material having a conductive contact therein.
7. The method of claim 5 , wherein forming the foundation material over each of the conductive material and the dielectric material comprises extending the foundational material over each of the conductive material and the dielectric material in a direction substantially perpendicular to that of the conductive material.
8. A method of forming a semiconductor device, comprising:
forming a dielectric material over a plurality of memory devices disposed on a wafer, the dielectric material at least partially surrounding the plurality of memory devices;
removing at least a portion of the dielectric material to form at least one opening therein extending through a major surface of the dielectric material;
forming a conductive material within the at least one opening in the dielectric material;
attaching another wafer to the major surface of the dielectric material; and
separating a portion of the another wafer to leave a foundation material overlying the major surface of the dielectric material and a surface of the conductive material.
9. The method of claim 8 , wherein forming a dielectric material over a plurality of memory devices disposed on a wafer comprises forming the dielectric material over at least one NAND array.
10. The method of claim 8 , wherein forming a dielectric material over a plurality of memory devices disposed on a wafer comprises forming a silicon dioxide material over the plurality of memory devices.
11. The method of claim 8 , wherein removing at least a portion of the dielectric material to form at least one opening therein comprises forming the at least one opening within the dielectric material having an average depth of between about five nanometers (5 nm) and about four hundred nanometers (400 nm).
12. The method of claim 8 , wherein removing at least a portion of the dielectric material to form at least one opening therein comprises forming the at least one opening within the dielectric material having an average width of between about one-half micron (0.5 μm) and about ten microns (10 μm).
13. The method of claim 8 , wherein forming a conductive material within the at least one opening in the dielectric material comprises forming a conductive material comprising at least one of polysilicon and a metal.
14. The method of claim 8 , wherein forming a conductive material within the at least one opening in the dielectric material comprises forming a conductive material comprising tungsten nitride.
15. The method of claim 8 , wherein forming a conductive material within the at least one opening in the dielectric material comprises:
forming a conductive material over the major surface of the dielectric material to fill the at least one opening; and
removing portions of the conductive material outside the at least one opening to render the major surface of the dielectric material substantially planar with the surface of the conductive material.
16. The method of claim 8 , further comprising implanting ions into the another wafer to form an implanted region therein.
17. The method of claim 16 , wherein attaching the another wafer to the major surface of the dielectric material comprises bonding the another wafer having an implanted region therein, the implanted region having a depth of between about eighty nanometers (80 nm) and about five hundred nanometers (500 nm).
18. The method of claim 8 , wherein separating a portion of the another wafer to leave a foundation material overlying the major surface of the dielectric material and a surface of the conductive material comprises separating the portion of the another wafer along an inner boundary of an implanted region therein.
19. The method of claim 8 , further comprising forming another plurality of memory devices on the foundation material, each of the memory devices of the another plurality on the foundation material overlying the plurality of memory devices disposed on the wafer.
20. The method of claim 19 , wherein forming another plurality of memory devices on the foundation material comprises forming an active region of the another plurality of memory devices in electrical contact with the conductive material.
21. The method of claim 19 , further comprising forming a conductive line extending from a bit line overlying the another plurality of memory devices and in electrical contact with a drain region of the another plurality of memory devices and a drain region of the plurality of memory devices.
22. The method of claim 19 , further comprising:
repeating forming, removing, attaching, and separating to form another foundation material overlying another dielectric material having another conductive material therein; and
forming a third plurality of memory devices on the another foundation material.