Memory array error correction apparatus, systems, and methods
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
1. An apparatus comprising:
an error code module operable to receive a plurality of data bursts to be written to a memory on a corresponding plurality of consecutive clock cycles, the error code module operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles; and
wherein the error code module is further operable to interleave operations of the read/modify/write processes such that read and write operations do not occur simultaneously.
2. The apparatus of claim 1 , wherein the error code module comprises a data combiner configured to generate a plurality of modified data bursts corresponding to the plurality of data bursts.
3. The apparatus of claim 2 , wherein the error code module further comprises a modified data register coupled to the data combiner and configured to store at least one modified data burst.
4. The apparatus of claim 2 , wherein the data combiner is further configured to generate the plurality of modified data bursts based, at least in part, on at least one data mask signal.
5. The apparatus of claim 1 , wherein the error code module is further configured to perform modify and write operations simultaneously.
6. The apparatus of claim 1 , wherein the read/modify/write process comprises determining if at least one of the plurality of data bursts includes an error.
7. A method, comprising:
receiving, at an error code module, a plurality of data bursts on a corresponding plurality of consecutive clock cycles;
performing, using the error code module, a read/modify/write process for each of the plurality of data bursts; and
wherein individual ones of the read/modify/write processes are performed within a time period no longer than a period of two cycles of the consecutive plurality of clock cycles and read and write operations of multiple of the read/modify/write processes do not occur simultaneously.
8. The method of claim 7 , wherein said performing a read/modify/write process comprises:
determining whether at least one of the plurality of data bursts includes an error.
9. The method of claim 8 , wherein said performing a read/modify/write process further comprises:
correcting the error responsive, at least in part, to at least one of the plurality of data bursts including the error.
10. The method of claim 7 , wherein said performing a read/modify/write process is based, at least in part, on a data mask signal.
11. The method of claim 7 , wherein said performing a read/modify/write process comprises:
receiving a set of read data;
combining the set of read data and a data burst to generate a set of combined data; and
outputting the set of combined data to a bus.
12. The method of claim 7 , wherein said performing a read/modify/write process comprises interleaving read operations, modify operations, and write operations.
13. The method of claim 7 , wherein performing a read/modify/write process comprises:
determining an address in a memory array to which at least one of the data bursts is to be written; and
reading data from the address.
14. A method, comprising:
receiving a first set of input data and a first address;
reading from the first address during a first clock cycle;
receiving a second set of data and a second address;
generating a first set of write data;
reading from the second address during a second clock cycle;
generating a second set of write data;
after reading from the second address, providing the first set of write data to a data bus before a third clock cycle; and
wherein said reading from the first address and said coupling the first set of write data do not occur simultaneously, and said reading from the second address and said providing the first set of write data do not occur simultaneously.
15. The method of claim 14 , wherein said generating a first set of write data is based, at least in part, on data corresponding to the first address.
16. The method of claim 14 , further comprising:
receiving a third set of input data and a third address; and
reading from the third address during a third clock cycle.
17. The method of claim 14 , wherein said generating a first set of write data comprises:
receiving an error correction code corresponding to the first address; and
determining whether a first set of data corresponding to the first address includes an error.
18. The method of claim 17 , further comprising:
correcting at least one error in the first set of data responsive to determining that the first set of data includes an error.
19. The method of claim 14 , wherein said reading from the first address comprises:
gating data corresponding to the first address from a local bus to a global bus.
20. The method of claim 14 , wherein the first clock cycle comprises a first clock transition and a second clock transition and said reading from the first address occurs during a time period between the first clock transition and the second clock transition.