IP Library › Granted Patent US 8,187,981
Granted Patent B2
US 8,187,981 · App. 11/870,641 · Granted May 29, 2012

Substrate processing method, substrate processing system, and computer-readable storage medium

Assignee: Tokyo Electron Limited
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Quick Facts
Patent No.
US 8,187,981
App. No.
11/870,641
Granted
May 29, 2012
Kind
B2
Abstract

A substrate processing method includes preparing a substrate having a low-k interlayer dielectric film as a to-be-etched film and a photoresist film, formed on the low-k interlayer insulating film, serving as an etching mask with a predetermined circuit pattern; etching the low-k interlayer insulating film through the photoresist film to form grooves and/or holes in the low-k interlayer insulating film; ashing the photoresist film by using hydrogen radicals generated by bring a hydrogen-containing gas into contact with a catalyst of a high temperature; and recovering damage to the low-k interlayer insulating film due to the ashing by supplying a specific recovery gas. The method further includes recovering damage to the low-k interlayer insulating film due to the etching by supplying a specific recovery gas.

Claims (14)

1. A substrate processing method, comprising:

preparing a substrate having a low-k interlayer dielectric film as a to-be-etched film and a photoresist film, formed on the low-k interlayer insulating film, serving as an etching mask with a predetermined circuit pattern;

etching the low-k interlayer insulating film through the photoresist film to form grooves and/or holes in the low-k interlayer insulating film;

ashing the photoresist film by using hydrogen radicals generated by bringing a hydrogen gas into contact with a catalyst of a high temperature, wherein the low-k interlayer insulating film is damaged by the ashing; and

recovering damage to the low-k interlayer insulating film due to the ashing by supplying a specific recovery gas,

wherein the low-k interlayer insulating film has a methyl group (—CH3) containing Si, and

wherein the damage is portions where the methyl group constituting the low-k interlayer insulating film is removed during the ashing.

2. The substrate processing method of claim 1 , wherein the etching, the ashing, and the recovering are performed within individual processing chambers, respectively.

3. The substrate processing method of claim 1 , wherein the etching, the ashing, and the recovering are performed within a same processing chamber.

4. The substrate processing method of claim 1 , wherein the ashing and the recovering are performed within the same processing chamber.

5. The substrate processing method of claim 1 , wherein the etching and the recovering are performed within a same processing chamber.

6. The substrate processing method of claim 1 , wherein the etching and the ashing are performed within a same processing chamber.

7. The substrate processing method of claim 1 , wherein recovering the damage is performed by means of a silylation processing employing a silylizing gas as the recovery gas.

8. The substrate processing method of claim 7 , wherein the silylizing gas is any one of TMDS (1,1,3,3-Tetramethyldisilazane), TMSDMA (Dimethylaminotrimethylsilane), and DMSDMA (Dimethylsilyldimethylamine).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2008
From: TOMIOKA, KAZUHIRO; KOBAYASHI, NOBUYOSHI; SAKURAGI, ISAMU; KUBOTA, KAZUHIRO
To: TOKYO ELECTRON LIMITED
Reel/Frame 021593/0238 →
Priority Claims (1)
JP 2006-278687 · Oct 12, 2006 · national
Continuity (2)
Provisional Application 60883256 · Jan 3, 2007
Related Publication 20090014414A1 · Jan 15, 2009