System and method for decoding commands based on command signals and operating state

1. A command decoder comprising:

a command signal latch having command nodes to which command signals are applied, the command signal latch configured to latch logic levels of the command signals;

bank control logic configured to provide a bank signal, the bank signal based, at least in part, on an operating state of a memory bank; and

a command decoder circuit coupled to the command signal latch, the command decoder circuit configured to receive the bank signal and further configured to generate internal control signals to perform a first operation according to latched logic levels of the command signals when the memory bank is in a first operating state and configured to generate internal control signals to perform a second operation according to the latched logic levels of the command signals when the memory bank is in a second operating state.

2. The command decoder of claim 1 wherein the first operation is selected from a first set of operations, the second operation is selected from a second set of operations having at least one different operation from the first set of operations, and the command decoder circuit is further configured to generate internal control signals to perform an operation selected from a third set of operations according to the latched logic levels of the command signals when the memory bank is in a third operating state.

3. The command decoder of claim 2 wherein the third operating state is entered from the first operating state in response to one of the operations of the first set of operations being selected.

4. The command decoder of claim 2 wherein the command decoder circuit is further configured to generate internal control signals to perform a third operation according to the first latched logic levels of the command signals when the memory bank is in the third operating state.

5. A memory device having a plurality of operating states at which a respective operation is performed, the memory device comprising:

an address bus;

a command bus to which command signals are applied;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a memory-cell array coupled to the address decoder and the read/write circuit; and

a command decoder coupled to the control bus, the address decoder, the read/write circuit, and the memory cell array, the command decoder configured to generate internal control signals for executing a requested operation, the command decoder comprising:

a command signal latch having command nodes coupled to the command bus, the command signal latch configured to latch logic levels of the command signals; and

a command decoder circuit coupled to the command signal latch, the command decoder circuit configured to receive a bank signal, the bank signal based, at least in part, on an operating state of a memory bank and the command decoder circuit further configured to generate internal control signals to perform a first operation according to latched logic levels of the command signals when the memory bank is in a first operating state and configured to generate internal control signals to perform a second operation according to the latched logic levels of the command signals when the memory bank is in a second operating state.

6. The memory device of claim 5 wherein the first operation is selected from a first set of operations, the second operation is selected from a second set of operations having at least one different operation from the first set of operations, and the command decoder circuit is further configured to generate internal control signals to perform an operation selected from a third set of operations according to the latched logic levels of the command signals when the memory bank is in a third operating state.

7. The memory device of claim 6 wherein the third operating state is entered from the first operating state in response to one of the operations of the first set of operations being selected.

8. The memory device of claim 5 wherein the command decoder circuit is further configured to generate internal control signals to perform a third operation according to the first latched logic levels of the command signals when the memory bank is in the third operating state.

9. A computer processing system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a memory device coupled to the processor and having a plurality of operating states at which a respective operation is performed, the memory device comprising,

an address bus;

a command bus to which command signals are applied;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a memory-cell array coupled to the address decoder and the read/write circuit; and

a command decoder coupled to the control bus, the address decoder, the read/write circuit, and the memory cell array, the command decoder configured to generate internal control signals for executing a requested operation, the command decoder comprising:

a command signal latch having command nodes coupled to the command bus, the command signal latch configured to latch logic levels of the command signals; and

a command decoder circuit coupled to the command signal latch, the command decoder circuit configured to receive a bank signal, the bank signal based, at least in part, on an operating state of a memory bank and the command decoder further configured to generate internal control signals to perform a first operation according to latched logic levels of the command signals when the memory bank is in a first operating state and configured to generate internal control signals to perform a second operation according to the latched logic levels of the command signals when the memory bank is in a second operating state.

10. The computer processing system of claim 9 wherein the first operation is selected from a first set of operations, the second operation is selected from a second set of operations having at least one different operation from the first set of operations, and the command decoder circuit is further configured to generate internal control signals to perform an operation selected from a third set of operations according to the latched logic levels of the command signals when the memory bank is in a third operating state.

11. The computer processing system of claim 10 wherein the third operating state is entered from the first operating state in response to one of the operations of the first set of operations being selected.

12. The computer processing system of claim 11 wherein the command decoder circuit is further configured to generate internal control signals to perform a third operation according to the first latched logic levels of the command signals when the memory bank is in the third operating state.

13. A method for decoding a command, comprising:

latching command signals, each signal having a respective logic level;

decoding the command signals based on the combination of logic levels;

receiving a bank signal from bank control logic, the bank signal based, at least in part, on an operating state of a memory bank;

determining a current operating state of a memory bank based, at least in part, on the bank signal;

generating a first set of internal control signals to perform a first operation based on the latched combination of logic levels of the command signals in response to the memory bank being in a first operating state; and

generating a second set of internal control signals to perform a second operation based on the latched combination of logic levels of the command signals in response to the memory bank being in a second operating state.

14. The method of claim 13 wherein determining the current operating state of the memory bank comprises determining whether the memory bank is in a bank active state or a bank inactive state.

15. The method of claim 14 wherein generating a first set of internal control signals to perform a first operation based on the latched combination of logic levels of the command signals comprises generating internal control signals to perform an operation resulting in the memory bank changing from the first operating state to the third operating state.

16. The method of claim 13 , further comprising monitoring a logic state of a signal and wherein generating the first set of internal control signals to perform a first operation comprises generating internal control signals to perform a first option of the first operation based on the latched combination of logic levels of the command signals and the signal having a first logic level and generating internal control signals to perform a second option of the first operation based on the latched combination of logic levels of the command signals and the signal having a second logic level.

17. The method of claim 16 wherein monitoring the logic state of the signal comprises monitoring the logic state of an address signal provided to the memory bank.