Three dimensional integrated deep trench decoupling capacitors

1. A method of forming an integrated circuit device, the method comprising:

forming a plurality of deep trench decoupling capacitors on a first substrate, the deep trench capacitors configured so as to have an upper capacitor electrode and a lower capacitor electrode such that a top surface of the upper capacitor electrode is substantially coplanar with a top surface of the lower capacitor electrode, wherein forming the plurality of deep trench decoupling capacitors on the first substrate comprises forming deep trenches within the first substrate, forming a doped region within the first substrate so as to define the lower capacitor electrode, and filling the deep trenches with a node dielectric material and a conductive fill material, the conductive fill material defining the upper capacitor electrodes;

forming a plurality of active circuit devices on a second substrate;

prior to bonding the second substrate to the first substrate, forming an inter-level dielectric layer on the first substrate, over the deep trench decoupling capacitors, and forming a plurality of vias within the inter-level dielectric layer, the vias providing electrical access to the upper electrodes and common lower electrode of the deep trench capacitors;

bonding the second substrate to the first substrate; and

forming electrical connections between the deep trench decoupling capacitors and the second substrate;

wherein the second substrate comprises a lower buried oxide layer and a silicon-on-insulator (SOI) layer formed on the buried oxide layer, with the active circuit devices formed on the SOI layer; and

wherein the bonding the second substrate to the first substrate further comprises thermal annealing to bond the buried oxide layer of the second substrate to oxide material of the inter-level dielectric layer of the first substrate.

2. The method of claim 1 , wherein forming the doped region within the first substrate comprises one or more of: ion implantation, arsenic silicon glass (ASG) film deposition and thermal drive-in, gas phase doping, and plasma immersion ion implantation.

3. The method of claim 1 , wherein the conductive fill material comprises one or more of: copper, tungsten, titanium nitride, silicide, carbon nanotube, amorphous carbon, and graphene.

4. The method of claim 1 , further comprising implanting the doped region with one or more of arsenic and phosphorous.