Timing, noise, and power analysis of integrated circuits
DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).
1. A method of compensating for manufacturing defects, comprising:
receiving a circuit design having a layout including a plurality of devices and a plurality of interconnects;
calculating a manufacturing variance of a device or interconnect, wherein the manufacturing variance is due to manufacturing effects of a neighboring device or interconnect on the device or interconnect;
modifying the circuit design to compensate for the manufacturing variance thereby generating a modified circuit design, wherein modifying the circuit design comprises modifying a cell within the circuit design by applying the manufacturing variance to the cell; and
storing the modified circuit design on a non-transitory computer readable storage medium;
wherein the manufacturing variance includes a capacitance variation, and wherein determining the capacitance variation comprises:
discretizing each interconnect into rectangular subsegments, wherein each subsegment is represented by at least one dimension;
discretizing the subsegments into a plurality of panels; and
calculating a coefficient of potential at each panel due to a unit charge placed on every other panel of the plurality of panels;
generating a potential matrix that includes coefficients of potential of all panels of each interconnect;
generating a capacitance matrix by inverting the potential matrix, the capacitance matrix including capacitances of all panels of the interconnect; and
determining capacitance between any pair of subsegments by summing capacitances between corresponding panels of the subsegments using information of the capacitance matrix.
2. The method of claim 1 , further comprising calculating a performance variance from simulated operation of the modified circuit design.
3. The method of claim 2 , wherein the performance variance includes timing.
4. The method of claim 3 wherein the timing includes a signal timing delay.
5. The method of claim 2 , wherein the performance variance includes signal integrity.
6. The method of claim 5 , wherein the signal integrity includes one or more of threshold voltage and output resistance of the devices.
7. The method of claim 2 , wherein the performance variance includes power consumption.
8. The method claim 7 , wherein power consumption includes off-state current drawn by the devices.
9. The method of claim 1 , comprising selecting a set of standard cells of the circuit design for which to determine a predicted variation, wherein the standard cells are selected from a plurality of standard cells that form the circuit design.
10. The method of claim 9 , comprising:
performing a timing analysis of the plurality of standard cells, the timing analysis generating a timing slack of each standard cell, the timing analysis performed before generating the modified circuit design; and
selecting for the set any standard cell for which the timing slack is below a first threshold.
11. The method of claim 9 , comprising:
performing a noise analysis of the plurality of standard cells, the noise analysis generating a noise value of each standard cell, the noise analysis performed before generating the modified circuit design; and
selecting for the set any standard cell for which the noise value exceeds a second threshold.
12. The method of claim 9 , comprising:
generating a modified standard cell by modifying a standard cell of the set within the circuit design to apply a parasitic variance and a variance to the standard cell;
generating a modified wire load by applying the parasitic variance to a wire load;
providing an input waveform to the modified standard cell and modified wire load; and
determining the predicted variation of the modified standard cell, the performance variance including a delay across the modified standard cell and an output waveform of the modified standard cell.
13. The method of claim 12 , comprising:
generating a second modified standard cell by modifying a second standard cell of the set within the circuit design to apply the parasitic variance and the device variance to the second standard cell of the circuit design, wherein the second modified standard cell is a next instance following the modified standard cell in a topological traversal of the design data;
providing the output waveform as the input waveform to the second modified standard cell and the modified wire load; and
determining the predicted variation of the second modified standard cell, the performance parameter including a second delay across the second modified standard cell and a second output waveform of the second modified standard cell.
14. The method of claim 12 , comprising:
applying a noise waveform to an input of the modified standard cell; and
determining the predicted variation of the modified standard cell, the performance variance including a noise magnitude at an output of the modified standard cell.
15. The method of claim 1 , comprising:
receiving a timing analysis of each standard cell of the circuit design, the timing analysis including a timing slack of each standard cell, the timing analysis performed before generating the modified circuit design; and
determining leakage power of each standard cell, the determining of leakage power performed before generating the modified circuit design.
16. The method of claim 15 , comprising:
generating a modified standard cell corresponding to each standard cell by modifying each standard cell within the circuit design to apply the second variance; and
determining a predicted variation by determining leakage power of each modified standard cell.
17. The method of claim 16 , comprising determining a leakage power variance of each standard cell.
18. The method of claim 17 , wherein determining the leakage power variance includes comparing the leakage power of each standard cell with the leakage power of each modified standard cell.
19. The method of claim 17 , wherein the leakage power variance includes a change in off-state current drawn by the standard cell.
20. The method claim 17 , wherein determining the leakage power variance comprises replacing the devices in the standard cell with a device model that predicts the off-state current drawn by the standard cell given the second variance.
21. The method of claim 16 , wherein determining leakage power of a cell including one or more of the standard cell and the modified standard cell comprises:
determining input logic states of the cell, the input logic states including at least one logic state of each input pin of the cell; and
determining average leakage power across the input logic states.
22. The method of claim 21 , wherein determining average leakage power across the input logic states comprises:
determining a leakage current drawn in each of the logic states; and
determining a probability of occurrence of each of the logic states.
23. The method of claim 22 , comprising:
multiplying the leakage current drawn in each of the logic states with the probability of occurrence of each of the logic states to form a weighted average leakage current for each logic state; and
summing the weighted average leakage current for all of the logic states.
24. The method of claim 1 , wherein the circuit design includes a drawing of a layout of the circuit.
25. A computer-aided design system configured to compensate for manufacturing defects, comprising:
a processor;
a memory connected to the processor; and
a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of:
receiving a circuit design having a layout including a plurality of devices and a plurality of interconnects;
calculating a manufacturing variance of a device or interconnect, wherein the manufacturing variance is due to manufacturing effects of a neighboring device or interconnect on the device or interconnect; and
modifying the circuit design to compensate for the manufacturing variance thereby generating a modified circuit design, wherein modifying circuit design comprises modifying at least one a cell within the circuit design by applying the manufacturing variance to the cell;
wherein the manufacturing variance includes a capacitance variation, and wherein the operation of determining the capacitance variation comprises:
discretizing each interconnect into rectangular subsegments, wherein each subsegment is represented by at least one dimension;
discretizing the subsegments into a plurality of panels; and
calculating a coefficient of potential at each panel due to a unit charge placed on every other panel of the plurality of panels;
generating a potential matrix that includes coefficients of potential of all panels of each interconnect;
generating a capacitance matrix by inverting the potential matrix, the capacitance matrix including capacitances of all panels of the interconnect; and
determining capacitance between any pair of subsegments by summing capacitances between corresponding panels of the subsegments using information of the capacitance matrix.