Semiconductor integrated circuit device with reduced leakage current
The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
1. A semiconductor integrated circuit device comprising:
a plurality of static type memory cells each having a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor, a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, a gate of the second P-channel MOS transistor and a gate of the second N-channel MOS transistor being connected to each other, and a drain of the second P-channel MOS transistor, a drain of the second N-channel MOS transistor, a gate of the first P-channel MOS transistor and a gate of the first N-channel MOS transistor being connected to each other;
a power line connected to sources of the first and second P-channel MOS transistors of the plurality of static type memory cells;
a source line connected to sources of the first and second N-channel MOS transistors of the plurality of static type memory cells; and
a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line,
wherein insulating layers used in the gates of the first P-channel MOS transistor, the second P-channel MOS transistor, the first N-channel MOS transistor, and the second N-channel MOS transistor have a thickness of 4 nm or less,
wherein the power voltage control circuit controls the power voltage so that the power voltage becomes a first voltage in an operating mode and a second voltage smaller than the first voltage in a standby mode to make a gate tunnel leak current flowing between the source and the gate of the first P-channel MOS transistor and a gate tunnel leak current flowing between the source and the gate of the second N-channel MOS transistor smaller in the standby mode rather than in the operating mode in case that the first P-channel MOS transistor and the second N-channel MOS transistor are in on-state, and
wherein a potential of a substrate of the first P-channel MOS transistor in the standby mode is equivalent to a potential of the source of the first P-channel MOS transistor in the standby mode, and a potential of a substrate of the second P-channel MOS transistor in the standby mode is equivalent to a potential of the source of the second P-channel MOS transistor in the standby mode.
2. The semiconductor integrated circuit device according to claim 1 ,
wherein the plurality of static type memory cells are selected to perform read or write data in the operating mode.
3. The semiconductor integrated circuit device according to claim 1 ,
wherein the operating mode and the standby mode are switched on a selecting signal.
4. The semiconductor integrated circuit device according to claim 1 ,
wherein each of the plurality of static type memory cells further comprises:
a first transfer N-channel MOS transistor coupled between one of a pair of data lines and the drains of the first P-channel MOS transistor and the first N-channel MOS transistor; and
a second transfer N-channel MOS transistor coupled between the other of the pair of data lines and the drains of the second P-channel MOS transistor and the second N-channel MOS transistor,
wherein potentials of the pair of data lines are set lower in the standby mode rather than a pre-charge potential in the operating mode, and
wherein, when the first and second transfer N-channel MOS transistors are in off-state, GIDL currents flowing through the first and second transfer N-channel MOS transistors are made smaller in the standby mode rather than in the operating mode, respectively.
5. The semiconductor integrated circuit device according to claim 1 ,
wherein, in the operating mode, a potential of the power line is set to be a first potential, a potential of the source line is set to be a second potential lower than the first potential, and potentials of substrates of the first and second N-channel MOS transistors are set to be the second potential equivalent to the potential of the source line,
wherein, in the standby mode, a potential of the power line is set to be the first potential, a potential of the source line is set to be a third potential lower than the first potential and higher than the second potential, and potentials of substrates of the first and second N-channel MOS transistors are set to be the second potential different from the potential of the source line.
6. The semiconductor integrated circuit device according to claim 5 ,
wherein the plurality of static type memory cells are selected to perform read or write data in the operating mode.
7. The semiconductor integrated circuit device according to claim 5 ,
wherein the operating mode and the standby mode are switched on a selecting signal.
8. The semiconductor integrated circuit device according to claim 5 ,
wherein each of the plurality of static type memory cells further comprises:
a first transfer N-channel MOS transistor coupled between one of a pair of data lines and the drains of the first P-channel MOS transistor and the first N-channel MOS transistor; and
a second transfer N-channel MOS transistor coupled between the other of the pair of data lines and the drains of the second P-channel MOS transistor and the second N-channel MOS transistor,
wherein potentials of the pair of data lines are set lower in the standby mode rather than a pre-charge potential in the operating mode; and
wherein, when the first and second transfer N-channel MOS transistors are in off-state, GIDL currents flowing through the first and second transfer N-channel MOS transistors are made smaller in the standby mode rather than in the operating mode, respectively.
9. A semiconductor integrated circuit device comprising:
a plurality of static type memory cells each having a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor and a second N-channel MOS transistor, a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, a gate of the second P-channel MOS transistor and a gate of the second N-channel MOS transistor being connected to each other, and a drain of the second P-channel MOS transistor, a drain of the second N-channel MOS transistor, a gate of the first P-channel MOS transistor and a gate of the first N-channel MOS transistor being connected to each other;
a power line connected to sources of the first and second P-channel MOS transistors of the plurality of static type memory cells;
a source line connected to sources of the first and second N-channel MOS transistors of the plurality of static type memory cells; and
a power voltage control circuit that controls a power voltage of the plurality of static type memory cells which is defined as a potential difference between the power line and the source line,
wherein insulating layers used in the gates of the first P-channel MOS transistor, the second P-channel MOS transistor, the first N-channel MOS transistor, and the second N-channel MOS transistor have a thickness of 4 nm or less,
wherein the power voltage control circuit controls the power voltage so that the power voltage becomes a first voltage in an operating mode and a second voltage smaller than the first voltage in a standby mode to make a gate tunnel leak current flowing between the source and the gate of the first P-channel MOS transistor and a gate tunnel leak current flowing between the source and the gate of the second N-channel MOS transistor smaller in the standby mode rather than in the operating mode in case that the first P-channel MOS transistor and the second N-channel MOS transistor are in on-state, and
wherein a potential of a substrate of the first N-channel MOS transistor in the standby mode is equivalent to a potential of the source of the first N-channel MOS transistor in the standby mode, and a potential of a substrate of the second N-channel MOS transistor in the standby mode is equivalent to a potential of the source of the second N-channel MOS transistor in the standby mode.
10. The semiconductor integrated circuit device according to claim 9 ,
wherein the plurality of static type memory cells are selected to perform read or write data in the operating mode.
11. The semiconductor integrated circuit device according to claim 9 ,
wherein the operating mode and the standby mode are switched on a selecting signal.
12. The semiconductor integrated circuit device according to claim 9 ,
wherein each of the plurality of static type memory cells further comprises:
a first transfer N-channel MOS transistor coupled between one of a pair of data lines and the drains of the first P-channel MOS transistor and the first N-channel MOS transistor; and
a second transfer N-channel MOS transistor coupled between the other of the pair of data lines and the drains of the second P-channel MOS transistor and the second N-channel MOS transistor,
wherein potentials of the pair of data lines are set lower in the standby mode rather than a pre-charge potential in the operating mode, and
wherein, when the first and second transfer N-channel MOS transistors are in off-state, GIDL currents flowing through the first and second transfer N-channel MOS transistors are made smaller in the standby mode rather than in the operating mode, respectively.
13. The semiconductor integrated circuit device according to claim 9 ,
wherein, in the operating mode, a potential of the source line is set to be a first potential, a potential of the power line is set to be a second potential higher than the first potential, and potentials of substrates of the first and second P-channel MOS transistors are set to be the second potential equivalent to the potential of the power line,
wherein, in the standby mode, a potential of the source line is set to be the first potential, a potential of the power line is set to be a third potential higher than the first potential and lower than the second potential, and potentials of substrates of the first and second P-channel MOS transistors are set to be the second potential different from the potential of the power line.
14. The semiconductor integrated circuit device according to claim 13 ,
wherein the plurality of static type memory cells are selected to perform read or write data in the operating mode.
15. The semiconductor integrated circuit device according to claim 13 ,
wherein the operating mode and the standby mode are switched on a selecting signal.
16. The semiconductor integrated circuit device according to claim 13 ,
wherein each of the plurality of static type memory cells further comprises:
a first transfer N-channel MOS transistor coupled between one of a pair of data lines and the drains of the first P-channel MOS transistor and the first N-channel MOS transistor; and
a second transfer N-channel MOS transistor coupled between the other of the pair of data lines and the drains of the second P-channel MOS transistor and the second N-channel MOS transistor,
wherein potentials of the pair of data lines are set lower in the standby mode rather than a pre-charge potential in the operating mode, and
wherein, when the first and second transfer N-channel MOS transistors are in off-state, GIDL currents flowing through the first and second transfer N-channel MOS transistors are made smaller in the standby mode rather than in the operating mode, respectively.