Integrated circuits having place-efficient capacitors and methods for fabricating the same

1. A method for fabricating an integrated circuit having a place-efficient capacitor comprising:

forming a dielectric layer overlying a conductive feature on a semiconductor substrate;

forming a via opening into the dielectric layer to expose a portion of the conductive feature;

etching a partial opening into the dielectric layer and positioned over the conductive feature;

depositing etch resistant particles overlying the dielectric layer and in the partial opening;

further etching the dielectric layer using the etch resistant particles as an etch mask to extend the partial opening;

forming a first conductive layer overlying the extended partial opening and electrically contacting the conductive feature;

forming a capacitor insulating layer overlying the first conductive layer; and

forming a second conductive layer overlying the insulating layer.

2. The method of claim 1 , wherein forming a via opening into the dielectric layer comprises:

forming and patterning an opening in a first photoresist layer; and

etching the via opening.

3. The method of claim 1 , further comprising after the forming a via opening and before etching a partial opening:

forming an organic planarization layer (OPL) overlying the dielectric layer including filling the via opening;

forming a second photoresist layer on the organic planarization layer (OPL); and

forming and patterning a second opening in the second photoresist layer and OPL layer.

4. The method of claim 1 , wherein depositing etch resistant particles comprises depositing etch resistant particles from the group selected from porous polymers, organic or inorganic particles, and combinations thereof.

5. The method of claim 1 , wherein depositing etch resistant particles comprises depositing etch resistant particles to distribute the etch resistant particles overlying the dielectric layer and in the partial opening.

6. The method of claim 1 , wherein forming a first conductive layer comprises forming a metal liner.

7. The method of claim 6 , wherein forming a first conductive layer comprises forming a lower capacitor electrode having an irregular surface area of the extended partial opening and via opening.

8. The method of claim 1 , wherein forming a second conductive layer overlying the insulating layer comprises forming a metal layer overlying the insulating layer including filling the extended partial opening with a metal fill material.

9. A method for fabricating an integrated circuit having a place-efficient capacitor comprising:

forming a dielectric layer overlying a conductive feature on a semiconductor substrate;

forming a via opening into the dielectric layer to expose a portion of the conductive feature;

filling the via opening with an organic planarization layer (OPL) material;

etching the dielectric layer to form a partial opening positioned over the conductive feature;

depositing etch-resistant particles over the dielectric layer in the partial opening;

further etching the dielectric layer around the etch-resistant particles to extend the partial opening forming an extended partial opening;

removing the etch-resistant particles and the OPL material within the via opening;

forming a lower capacitor electrode comprising a metal liner within the via opening and the extended partial opening;

forming a capacitor insulating layer overlying the metal liner; and

forming an upper capacitor electrode comprising filling the via opening and the extended partial opening with a metal fill material.

10. The method of claim 9 , wherein forming a via opening into the dielectric layer comprises:

forming and patterning an opening in a first photoresist layer; and

etching the via opening.

11. The method of claim 9 , further comprising after filling the via opening and before etching the dielectric layer:

forming a second photoresist layer on the OPL material; and

forming and patterning a second opening in the second photoresist layer and OPL material, the partial opening extending the second opening.

12. The method of claim 9 , wherein etching the dielectric layer to form a partial opening comprises etching to form a partial opening transverse to the via opening.

13. The method of claim 9 , wherein depositing etch resistant particles comprises depositing etch resistant particles from the group selected from porous polymers, organic or inorganic particles, and combinations thereof.

14. The method of claim 13 , wherein depositing etch resistant particles comprises depositing etch-resistant inorganic particles selected from the group consisting of platinum, gold, carbon, and combinations thereof.

15. The method of claim 13 , wherein depositing etch resistant particles comprises depositing etch resistant particles with an area coverage of about 20% to about 60%.

16. The method of claim 9 , wherein forming a lower capacitor electrode comprises forming the lower capacitor electrode having an irregular surface area of the extended partial opening and via opening.

17. The method of claim 9 , wherein forming an upper capacitor electrode comprises forming a metal layer overlying the capacitor insulating layer including filling the via opening and the extended partial opening with the metal fill material of the metal layer.