IP Library › Granted Patent US 8,237,216
Granted Patent B2
US 8,237,216 · App. 12/915,578 · Granted Aug 7, 2012

Apparatus having a lanthanum-metal oxide semiconductor device

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,237,216
App. No.
12/915,578
Granted
Aug 7, 2012
Kind
B2
Abstract

Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed.

Claims (24)

1. An apparatus comprising:

a substrate; and

a dielectric material disposed above the substrate, the dielectric material containing a region of lanthanum-metal oxide, the lanthanum-metal oxide having an oxide composition without nitrogen, the metal of the lanthanum-metal oxide being a metal other than lanthanum, the lanthanum-metal oxide doped with a lanthanide other than lanthanum.

2. The apparatus of claim 1 , wherein the lanthanum-metal oxide is structured as one or more monolayers.

3. The apparatus of claim 1 , wherein the dielectric material consists essentially of the region.

4. The apparatus of claim 1 , wherein the dielectric material includes a stack of insulating materials in addition to the region.

5. The apparatus of claim 1 , wherein the dielectric material includes a dielectric metal oxide.

6. The apparatus of claim 5 , wherein the dielectric metal oxide includes a metal different from the metal in the lanthanum-metal oxide.

7. The apparatus of claim 5 , wherein the dielectric metal oxide includes a lanthanide oxide consisting essentially of the lanthanide of the lanthanide oxide and oxygen.

8. The apparatus of claim 1 , wherein the dielectric material includes a dielectric nitride or a dielectric metal silicate.

9. The apparatus of claim 1 , wherein the dielectric material includes an insulating non-lanthanide oxide.

10. The apparatus of claim 1 , wherein the apparatus includes an interfacial region connecting the dielectric material to the substrate, the interfacial region including a lanthanum silicate, a metal silicate comprising the metal of the lanthanum-metal oxide, or a lanthanum metal silicate comprising the metal of the lanthanum-metal oxide.

11. The apparatus of claim 1 , wherein the apparatus includes a metal electrode contacting the lanthanum-metal oxide, the metal electrode having a composition such that the metal electrode essentially does not undergo an interface reaction with the lanthanum-metal oxide.

12. The apparatus of claim 11 , wherein the metal electrode contacting the lanthanum-metal oxide includes ruthenium.

13. The apparatus of claim 1 , wherein the metal of the lanthanum-metal oxide is aluminum.

14. The apparatus of claim 1 , wherein the dielectric material is disposed as a gate insulator in a silicon complementary metal-oxide semiconductor (CMOS) device.

15. The apparatus of claim 1 , wherein the dielectric material is disposed as a capacitor in an integrated circuit, the integrated circuit configured as an analog integrated circuit, a radio frequency (RF) integrated circuit, or a mixed signal integrated circuit.

16. The apparatus of claim 1 , wherein the dielectric material is disposed as a gate insulator or an inter-gate insulator in a transistor.

17. An apparatus comprising:

a substrate; and

a memory device disposed on the substrate, the memory device having a dielectric material disposed above the substrate, the dielectric material containing a region of lanthanum-metal oxide, the lanthanum-metal oxide having an oxide composition without nitrogen, the metal of the lanthanum-metal oxide being a metal other than lanthanum, the lanthanum-metal oxide doped with a lanthanide other than lanthanum.

18. The apparatus of claim 17 , wherein the dielectric material is disposed as a gate insulator or an inter-gate insulator in a transistor of a flash memory device.

19. The apparatus of claim 17 , wherein the dielectric material is disposed as a charge-storing nanolaminate dielectric in a flash memory device.

20. The apparatus of claim 17 , wherein the dielectric material is disposed as a capacitor dielectric in a capacitor in a dynamic random access memory.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Continuation 11608286 · Dec 8, 2006
Division 10930167 · Aug 31, 2004
Related Publication 20110037117A1 · Feb 17, 2011