Granted Patent B2

US 8,242,561 · App. 12/702,684 · Granted Aug 14, 2012

Abstract

Claims (58)

1. A field effect device comprising:

a channel region disposed on a silicon on insulator (SOI) layer;

a gate portion disposed on the channel region;

a source region disposed above the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device;

a silicide portion that includes the horizontal surface and vertical surface of the source region;

a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region; and

a drain region connected to the channel region disposed on the SOI layer.

2. The device of claim 1 , wherein the drain region includes:

a silicide portion that includes a horizontal surface and a vertical surface of the drain region, the vertical surface arranged perpendicular to a linear axis of the device; and

the device includes a second contact including a metallic material in contact with the horizontal surface and vertical surface of the drain region.

3. The device of claim 1 , wherein the gate portion includes:

a high K layer disposed on the SOI layer;

a metal gate disposed on the high K layer; and

a polysilicon layer disposed on the metal gate.

4. The device of claim 1 , wherein the field effect device is a FinFET device, and the channel region, the source region, and the drain region define a fin of a FinFET device.

5. The device of claim 4 , wherein the gate portion includes:

first gate dielectric layer disposed on the channel region;

a silicon oxide layer disposed on the first gate dielectric layer;

a second gate dielectric layer disposed on the silicon oxide layer; and

a metal layer disposed on the second gate dielectric layer.

6. A method for forming a field effect device comprising:

forming a gate portion on a silicon on insulator (SOI) layer, the SOI layer arranged on a substrate;

forming spacers on the SOI layer on opposing sides of the gate stack portion;

forming a silicon layer on the SOI layer;

removing portions of the silicon layer and the SOI layer and exposing the substrate to define a source region having horizontal surface and a vertical surface;

forming a silicide portion on the horizontal surface and the vertical surface of the source region; and

depositing a metallic material in contact with the horizontal surface and vertical surface of the silicide portion of the source region.

7. The method of claim 6 , wherein the method further comprises:

removing portions of the silicon layer and the SOI layer to define a drain region having a horizontal surface and a vertical surface;

forming a silicide portion on the horizontal surface and vertical surface of the drain region; and

depositing a metallic material in contact with the horizontal surface and vertical surface of the silicide portion of the drain region.

8. The method of claim 6 , wherein the removed portions of the silicon layer and the SOI layer to define a source region having a horizontal surface and a vertical surface are removed by an etching process.

9. The method of claim 6 , wherein the horizontal surface and vertical surface of the source region are arranged orthogonally.

10. The method of claim 6 , wherein the gate portion includes:

a high K layer disposed on the SOI layer;

a metal gate disposed on the high K layer; and

a polysilicon layer disposed on the metal gate.

11. A method for forming a field effect device comprising:

forming a FinFET body of the device above a silicon on insulator (SOI) layer, the body having a source region, a drain region, and a channel region extending therebetween;

forming a gate portion on the channel region;

forming a spacer that covers the gate portion, a portion of the source region, a portion of the drain region, and a portion of the SOI layer;

removing a portion of the source region to define an exposed vertical surface of the source region perpendicular to a longitudinal axis of the body; and

forming a silicide portion on the exposed vertical surface of the source region.

12. The method of claim 11 , wherein the method further includes:

removing a portion of the drain region to define a vertical surface of the drain region perpendicular to a longitudinal axis of the body; and

forming a silicide portion on the vertical surface of the drain region.

13. The method of claim 11 , wherein the method further includes:

forming a silicide portion on a horizontal surface of the source region, the silicide portion on the horizontal surface of the source region is orthogonal to the silicide portion on the exposed vertical surface of the source region.

14. The method of claim 13 , wherein the method further includes depositing a metallic material in contact with the vertical surface and the horizontal surface of the silicide portion of the source region.

15. The method of claim 12 , wherein the method further includes:

forming a silicide portion on a horizontal surface of the drain region, the silicide portion on the horizontal surface of the source region is orthogonal to the silicide portion on the vertical surface of the drain region.

16. The method of claim 15 , wherein the method further includes depositing a metallic material in contact with the vertical surface and the horizontal surface of the silicide portion of the drain region.

17. The method of claim 11 , wherein the gate portion includes:

a high K layer disposed on the SOI layer;

a metal gate disposed on the high K layer; and

a polysilicon layer disposed on the metal gate.

18. The method of claim 11 , wherein the removed portion of the source region to define a vertical surface of the source region perpendicular to a longitudinal axis of the body is removed by an etching process.

19. The method of claim 11 , wherein the gate portion is formed by: disposing first gate dielectric layer on the channel region; disposing a silicon oxide layer on the first gate dielectric layer; disposing a second gate dielectric layer on the silicon oxide layer; and disposing a metal layer on the second gate dielectric layer.

Assignments (8)