IP Library Granted Patent US 8,258,055
Granted Patent B2
US 8,258,055 · App. 12/832,168 · Granted Sep 4, 2012

Method of forming semiconductor die

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,258,055
App. No.
12/832,168
Granted
Sep 4, 2012
Kind
B2
Abstract

An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.

Claims (30)

1. A method of forming a semiconductor die comprising:

providing a substrate;

forming a bond pad over the substrate;

depositing an under bump metallurgy (UBM) layer over the bond pad;

forming a copper pillar over the UBM layer;

depositing a nickel layer over the copper pillar, wherein an interface is defined between the nickel layer and the copper pillar;

depositing a solder material over the nickel layer;

etching the nickel layer and the copper pillar in an aqueous solution comprising 55% to 85% H 3 PO 4 by volume, less than 1% Azole-based compound by volume, and less than 1% Sn by volume; and

etching the UBM layer after the step of etching the nickel layer and the copper pillar.

2. The method of claim 1 , wherein the step of etching in the aqueous solution is performed at a temperature in the range of 30° C. and 70° C.

3. The method of claim 1 , wherein the aqueous solution comprises about 70% H 3 PO 4 by volume.

4. The method of claim 1 , wherein after the two etching steps the etched copper pillar adjacent to the interface has a first width, the etched nickel layer adjacent to the interface has a second width, and a ratio of the second width to the first width is between about 0.93 to about 0.99.

5. The method of claim 1 , wherein the solder material comprises lead free solder.

6. The method of claim 1 , wherein the etching of the UBM layer comprises wet etching, dry etching, or a combination thereof.

7. The method of claim 1 , wherein the conductive pillar has a concave shape.

8. A method of forming a semiconductor die comprising:

providing a substrate;

forming a bond pad over the substrate;

depositing an under bump metallurgy (UBM) layer comprising copper over the bond pad;

depositing a nickel layer over the UBM layer;

depositing a solder material over the nickel layer; and

etching the nickel layer and the UBM layer in an aqueous solution comprising 36% to 42% H 3 PO 4 by volume, 2% to 3% HNO 3 by volume, 44% to 49% CH 3 COOH by volume, and 2% to 3% Sn by volume.

9. The method of claim 8 , wherein the step of etching in the aqueous solution is performed at a temperature in the range of 30° C. and 45° C.

10. The method of claim 8 , wherein the aqueous solution comprises about 40% H 3 PO 4 by volume.

11. The method of claim 8 , further comprising forming a copper pillar over the UBM layer and underlying the nickel layer, thereby forming an interface between the copper pillar and the nickel layer.

12. The method of claim 11 , wherein the copper pillar adjacent to the interface has a first width, the nickel layer adjacent to the interface has a second width, and a ratio of the second width to the first width is between about 0.93 to about 1.07.

13. The method of claim 8 , wherein the UBM layer further comprises titanium.

14. The method of claim 13 , further comprising etching the UBM layer comprising titanium in an aqueous solution comprising less than 1% HF by volume.

15. The method of claim 13 , further comprising etching the UBM layer comprising titanium in a gaseous environment containing Cl2, CFx or CHFx.

16. The method of claim 8 , wherein the solder material comprises lead free solder.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2010
From: HWANG, CHIEN LING; HUANG, YING-JUI; LIM, ZHENG-YI; LEI, YI-YANG; LIN, CHENG-CHUNG; LIU, CHUNG-SHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024649/0853 →
Continuity (1)
Related Publication 20120007230A1 · Jan 12, 2012