PLL circuit and optical disc apparatus
A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data.
1. A PLL circuit comprising:
a polyphase reference clock output circuit that outputs a plurality of reference clocks with different phases, the polyphase reference clock output circuit comprising a plurality of delay cells including a differential input and a differential output, the plurality of delay cells being connected in series, and the reference clock is output from each output of the plurality of delay cells;
a polyphase frequency divider circuit that outputs a plurality of divided clocks, the plurality of divided clocks being obtained by dividing frequencies of the plurality of reference clocks by a predetermined value;
a selection switch circuit that selects one of the plurality of reference clocks or one of the plurality of divided clocks, and outputs the selected clock as a selected clock;
a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, the output clock including a frequency that fluctuates according to a value of frequency control input data, and the ideal phase being calculated according to the output clock and the value of the frequency control input data; and
a selection circuit that selects and outputs the output clock, the output clock being synchronized with one of the plurality of divided clocks according to the delay amount data.
2. The PLL circuit according to claim 1 , wherein the polyphase divider circuit sets a phase difference between divided clocks of the plurality of divided clocks to be same as a phase difference between reference clocks of the plurality of reference clocks.
3. The PLL circuit according to claim 1 , wherein the digital VCO increases a frequency of the output clock as the value of the frequency control data increases.
4. The PLL circuit according to claim 1 , further comprising a first frequency divider circuit that is connected with the PLL circuit, and outputs a first clock, the first clock being obtained by dividing a clock frequency of the plurality of reference clocks or the plurality of divided clocks by a predetermined value.
5. The PLL circuit according to claim 4 , wherein the first frequency divider circuit outputs a first clock, the first clock being obtained by fractionally dividing the frequency of the plurality of reference clocks or the plurality of divided clocks.
6. The PLL circuit according to claim 5 , wherein the first frequency divider circuit outputs the first clock divided by 1.5 using clocks with a 270 phase shift among the plurality of reference clocks or the plurality of divided clocks.
7. The PLL circuit according to claim 4 , wherein
the PLL circuit is used in an optical disc apparatus, and
the optical disc apparatus comprises:
the PLL circuit;
the first frequency divider circuit; and
a logic circuit,
wherein the logic circuit operates using the first clock output from the first frequency divider circuit as a system clock.
8. An optical disc apparatus comprising:
the PLL circuit according to claim 4 ;
the first frequency divider circuit; and
a logic circuit,
wherein the logic circuit operates using the first clock output from the first frequency divider circuit as a system clock.
9. A PLL circuit comprising:
a polyphase reference clock output circuit that outputs a plurality of reference clocks with different phases;
a polyphase frequency divider circuit that outputs a plurality of divided clocks, the plurality of divided clocks being obtained by dividing frequencies of the plurality of reference clocks by a predetermined value, the polyphase frequency divider circuit being configured to set a phase difference between divided clocks of the plurality of divided clocks to be same as a phase difference between reference clocks of the plurality of reference clocks;
a selection switch circuit that selects one of the plurality of reference clocks or one of the plurality of divided clocks, and outputs the selected clock as a selected clock;
a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, the output clock including a frequency that fluctuates according to a value of frequency control input data, and the ideal phase being calculated according to the output clock and the value of the frequency control input data; and
a selection circuit that selects and outputs the output clock, the output clock being synchronized with one of the plurality of divided clocks according to the delay amount data, wherein the polyphase divider circuit comprises:
a plurality of first latch circuits that are connected in series, latch an output of a previous stage in response to each of the plurality of reference clocks as a trigger signal, and output the plurality of divided clocks from each output terminal; and
a first inverter circuit,
wherein the first inverter inputs an output of a first stage latch circuit among the plurality of first latch circuits, and outputs the output to the first stage latch circuit.
10. A PLL circuit comprising:
a polyphase reference clock output circuit that outputs a plurality of reference clocks with different phases;
a polyphase frequency divider circuit that outputs a plurality of divided clocks, the plurality of divided clocks being obtained by dividing frequencies of the plurality of reference clocks by a predetermined value;
a selection switch circuit that selects one of the plurality of reference clocks or one of the plurality of divided clocks, and outputs the selected clock as a selected clock;
a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, the output clock including a frequency that fluctuates according to a value of frequency control input data, and the ideal phase being calculated according to the output clock and the value of the frequency control input data; and
a selection circuit that selects and outputs the output clock, the output clock being synchronized with one of the plurality of divided clocks according to the delay amount data, wherein the selection circuit comprises:
a plurality of second latch circuits that are connected with the plurality of divided clocks respectively; and
a selector that selects one of the plurality of delay clocks output from each of the plurality of second latch circuits,
wherein the plurality of second latch circuits latch the output clock in response to a corresponding divided clock as a trigger signal.