Method of forming package-on-package and device related thereto
Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
1. A method of forming a semiconductor package, comprising:
forming a plurality of through silicon vias (TSVs) through an upper surface of a wafer, the wafer having a plurality of first semiconductor chips, the plurality of TSVs being formed to have lower ends buried in the wafer and upper ends exposed by one surface of the wafer;
forming an encapsulant on the wafer using a wafer level molding process, the encapsulant being formed to cover the upper ends of the TSVs;
partially removing a lower surface of the molded wafer to expose the lower ends of the TSVs;
forming openings through the encapsulant after the partially removing a lower surface of the molded wafer, the openings being aligned on the upper ends of the TSVs;
dividing the encapsulant with the openings and the wafer to form a plurality of first semiconductor packages; and
stacking a second semiconductor package on a first semiconductor package selected from the plurality of first semiconductor packages, the second semiconductor package being electrically connected to the TSVs.
2. The method according to claim 1 , wherein the plurality of first semiconductor packages have substantially a same width as the plurality of first semiconductor chips, and the second semiconductor package has a width one of equal to and smaller than that of the first semiconductor package selected from the plurality of first semiconductor packages.
3. The method according to claim 1 , further comprising:
forming internal connection terminals at the upper ends of the TSVs, wherein the internal connection terminals are one of a conductive bump, a solder ball, a conductive spacer, a pin grid array (PGA), a lead grid array (LGA), and a combination thereof, and the internal connection terminals are formed before forming the encapsulant.
4. The method according to claim 3 , wherein the internal connection terminals are disposed in the encapsulant.
5. The method according to claim 3 , wherein a top of the internal connection terminals is lower than a top of the encapsulant.
6. The method according to claim 1 , further comprising:
attaching a third semiconductor package between the first semiconductor package selected from the plurality of first semiconductor packages and the second semiconductor package, the third semiconductor package being selected from the plurality of first semiconductor packages.
7. The method according to claim 1 , further comprising:
attaching a printed circuit board to a lower part of the first semiconductor package selected from the plurality of first semiconductor packages, wherein the printed circuit board has a width one of equal to and smaller than that of the first semiconductor package selected from the plurality of first semiconductor packages, and the second semiconductor package is electrically connected to the printed circuit board via the TSVs.
8. The method of claim 1 wherein the stacking comprises:
providing the second semiconductor package including at least one external contact terminal and at least one second semiconductor chip; and
inserting the at least one external contact terminal into the at least one of the openings of one of the first semiconductor packages to electrically connect the at least one second semiconductor chip to the first semiconductor chip.
9. The method of forming a semiconductor package of claim 8 , wherein the at least one of the openings extends through the encapsulant of the first semiconductor package, and the at least one external contact terminal is a plurality of external contact terminals, the plurality of external contact terminals corresponding to the openings such that each of the openings is mated with one of the external contact terminals of the plurality of external contact terminals.
10. The method of forming a semiconductor package of claim 9 , wherein the plurality of TSVs correspond to the openings such that each TSV of the plurality of TSVs is electrically connected to one of the external contact terminal of the plurality of external contact terminals.
11. The method of forming a semiconductor package of claim 10 , wherein the openings expose the plurality of TSVs.
12. A method of forming a semiconductor package, comprising:
forming a plurality of through silicon vias (TSVs) through an upper surface of a wafer, the wafer having a plurality of semiconductor chips, the plurality of TSVs being formed to have lower ends buried in the wafer and upper ends exposed by the upper surface of the wafer;
partially removing a lower surface of the wafer to expose the lower ends of the TSVs;
forming an encapsulant on at least one of the upper and lower surfaces of the wafer exposing the lower ends of the TSVs after the partially removing a lower surface of the wafer, using a wafer level molding process;
forming openings passing through the encapsulant, the openings being aligned with the TSVs;
dividing the encapsulant with the openings and the wafer to form a plurality of first semiconductor packages; and
stacking a second semiconductor package on a first semiconductor package selected from the plurality of first semiconductor packages, wherein the second semiconductor package is electrically connected to the TSVs.