Electronic devices including carbon-based films having sidewall liners, and methods of forming such devices

1. A method of forming a microelectronic structure, the method comprising:

forming a layerstack, the layerstack comprising:

a resistivity-switchable layer and

a top electrode above and in contact with the resistivity-switchable layer;

etching the layerstack to have a pattern including sidewalls;

forming a dielectric sidewall liner in contact with the sidewalls of the layerstack; and

forming a dielectric fill layer around the dielectric sidewall liner,

wherein the resistivity-switchable layer includes a carbon-based material, and the dielectric sidewall liner includes an oxygen-poor dielectric material.

2. The method of claim 1 , further comprising:

planarizing to co-expose the dielectric fill layer, the dielectric sidewall liner, and the top electrode.

3. The method of claim 2 , wherein:

the pattern comprises a pillar, and

forming the dielectric sidewall liner comprises forming a pre-dielectric fill liner around the pillar.

4. The method of claim 2 , wherein:

the dielectric fill layer comprises an oxide, and

the dielectric sidewall liner comprises a nitride.

5. The method of claim 1 , further comprising:

forming a steering element in electrical series with the layerstack;

wherein the layerstack further comprises a bottom electrode below and in contact with the resistivity-switchable layer.

6. The method of claim 5 , wherein:

the steering element comprises a diode.

7. The method of claim 5 , wherein:

the layerstack comprises part of a memory cell.

8. The method of claim 1 , wherein:

the carbon-based material comprises carbon nanotubes.

9. The method of claim 1 , wherein:

the oxygen-poor dielectric material comprises silicon and nitrogen.

10. The method of claim 1 , wherein:

the resistivity-switchable layer of carbon-based material comprises a carbon-based liner above and in contact with a carbon-based active layer.

11. A microelectronic structure comprising:

a layerstack, the layerstack having a pattern including sidewalls, and the layerstack comprising:

a resistivity-switchable layer disposed above and in contact with a bottom electrode, and

a top electrode above and in contact with the resistivity-switchable layer;

a dielectric sidewall liner in contact with the sidewalls of the layerstack;

a dielectric fill layer around the dielectric sidewall liner,

wherein the resistivity-switchable layer includes a carbon-based material, and the dielectric sidewall liner includes an oxygen-poor dielectric material.

12. The microelectronic structure of claim 11 , wherein:

the pattern comprises a pillar, and

the dielectric sidewall liner comprises a pre-dielectric-fill liner around the pillar.

13. The microelectronic structure of claim 11 , wherein:

the dielectric fill layer comprises an oxide, and

the dielectric sidewall liner comprises a nitride.

14. The microelectronic structure of claim 11 , further comprising:

a steering element in electrical series with the layerstack;

wherein the layerstack further comprises a bottom electrode below and in contact with the resistivity-switchable layer.

15. The microelectronic structure of claim 14 , wherein:

the steering element comprises a diode.

16. The microelectronic structure of claim 14 , wherein:

the layerstack comprises part of a memory cell.

17. The microelectronic structure of claim 11 , wherein:

the carbon-based material comprises carbon nanotubes.

18. The microelectronic structure of claim 11 , wherein:

the oxygen-poor dielectric material comprises silicon and nitrogen.

19. The microelectronic structure of claim 11 , wherein:

the resistivity-switchable layer of carbon-based material comprises a carbon-based liner above and in contact with a carbon-based active layer.

20. A method of forming a microelectronic structure, the method comprising:

forming a layerstack comprising a carbon-based resistivity-switchable layer, and a top electrode above and in contact with the resistivity-switchable layer;

etching the layerstack to have a pattern including sidewalls;

forming a dielectric sidewall liner in contact with the sidewalls of the layerstack; and

forming a dielectric fill layer around the dielectric sidewall liner,

wherein the dielectric sidewall liner includes an oxygen-poor dielectric material.

21. The method of claim 20 , further comprising:

planarizing to co-expose the dielectric fill layer, the dielectric sidewall liner, and the layerstack.

22. The method of claim 21 , wherein:

the pattern comprises a pillar, and

forming the dielectric sidewall liner comprises forming a pre-dielectric fill liner around the pillar.

23. The method of claim 21 , wherein:

the dielectric fill layer comprises an oxide, and

the dielectric sidewall liner comprises a nitride.

24. The method of claim 20 , wherein:

the oxygen-poor dielectric material comprises silicon and nitrogen.

25. The method of claim 20 , wherein:

forming the dielectric sidewall liner comprises depositing the dielectric sidewall by plasma enhanced chemical vapor deposition (PECVD).

26. The method of claim 20 , wherein:

forming the dielectric sidewall liner comprises depositing the dielectric sidewall by atomic layer deposition (ALD).

27. The method of claim 26 , wherein:

the dielectric sidewall liner comprises silicon nitride; and

depositing the silicon nitride comprises performing an ALD silicon cycle and an ALD nitrogen cycle.

28. The method of claim 27 , wherein:

depositing the silicon nitride further comprises performing an anneal between performing the ALD silicon cycle and performing the ALD nitrogen cycle.

29. The method of claim 27 , wherein:

the ALD silicon cycle is performed using first chamber conditions, the ALD nitrogen cycle is performed using second chamber conditions, and the first chamber conditions differ from the second chamber conditions.