Data processor device having trace capabilities and method
In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.
1. A method comprising:
storing a count having a value of greater than one at a reprogrammable storage location;
(a) determining that an event has occurred in response to determining that a number of instruction cycles equal to the count have been executed by the data processor or in response to determining that a number of instructions equal to the count have been processed by the data processor;
(b) in response to determining the event has occurred, storing information at a trace buffer of the integrated circuit, the information related to instruction processing of an active instruction by the data processor;
(c) determining if the trace buffer has obtained a defined level of fullness;
(d) repeating (a) and (b) until the trace buffer obtains a defined level of fullness;
(e) in response to the trace buffer obtaining the defined level of fullness, halting operation of the data processor to prevent a next instruction from being executed; and
(f) in response to receiving an indicator to resume instruction execution, resuming instruction execution at the next instruction and repeating (a)-(f).
2. The method of claim 1 , wherein the event has occurred in response to determining that the number of instruction cycles equals the count.
3. The method of claim 2 further comprising modifying the count subsequent to determining the event has occurred.
4. The method of claim 1 wherein the information is instruction trace information indicating status information related to the execution of instructions.
5. The method of claim 1 further comprising:
in response to external control information, providing information stored at the trace buffer serially through a single pin.
6. The method of claim 5 , wherein the external control information is received serially through the single pin.
7. The method of claim 1 , wherein the event is a periodic event.
8. The method of claim 1 , wherein the event is indicative of the processing of instructions, and the processing of instructions is not a periodic event.
9. The method of claim 1 further comprising:
in response to determining the event has occurred, triggering a CPU event at a central processor unit (CPU) of the data processor that results in the CPU performing an instruction fetch.
10. The method of claim 9 , wherein triggering the CPU event at the CPU is accomplished by sending a command to the CPU.
11. The method of claim 1 , wherein the information stored at the trace buffer is dynamic program trace information in response to a re-programmable trace information indicator having a first state, and the information stored at the trace buffer is dynamic program profile information, and not dynamic trace information, in response to the re-programmable trace information indicator having a second state.
12. A data processor device comprising:
a central processor unit (CPU) comprising an input, the CPU to receive and execute instructions, and to halt execution of instructions in response to receiving an asserted first signal at the input;
a trace buffer;
a register set comprising a first re-programmable location to store a value greater than one; and
a control module comprising
a trace controller comprising an output, the trace controller to assert a second signal at the output in response to determining that the number of new active instructions processed is equal to the value stored at the register set; and
a memory controller comprising an input coupled to the output of the trace controller, and an output coupled to the input of the CPU, the memory controller to store information at the trace buffer in response to the second signal at the output of the trace controller being asserted, the information related to instruction processing of an active instruction at the CPU, the memory controller to assert the first signal at the output in response to the trace buffer obtaining a defined level of fullness, the asserted first signal to be received at the input of the CPU.
13. The data processor device of claim 12 further comprising:
the register set comprising a second re-programmable location, where the trace controller is to assert the second signal in response to the second re-programmable location storing a re-programmable indicator, and the memory controller is to overwrite information at the trace buffer controller in response to the second re-programmable location storing the re-programmable indicator.
14. The method of claim 12 , wherein the memory controller is further to provide an event that results in the CPU performing an instruction fetch, and the information stored at the trace buffer includes address information based upon the performed instruction fetch.
15. A method comprising:
determining if an event has occurred at a data processor of an integrated circuit, the occurrence of the event in response to determining that a number of instruction cycles have been executed by the data processor, when the number matches a value greater than one and is at a re-programmable storage location or that a number of instructions have been processed by the data processor matches the value;
in response to determining, based upon a re-programmable indicator, that the data processor is in a first mode of operation,
(a) for each instruction executed at a central processor unit (CPU), storing dynamic program trace information associated with each executed instruction at a trace buffer until the trace buffer obtains defined level of fullness;
(b) halting execution of instructions at the CPU in response to the trace buffer obtaining the defined level of fullness;
(c) providing information stored at the trace buffer to a single pin external interface in response to decoding a first debug command received at the single pin external interface;
(d) resuming execution of instructions at the trace buffer in response to decoding a second debug command received at the single pin external interface; and
(e) repeating (a)-(e); and
in response to determining the data processor is in a second mode of operation based upon the re-programmable indicator,
for each instruction executed at the CPU, storing dynamic program trace information associated with each executed instruction at the trace buffer overwriting data when the trace buffer surpasses the defined level of fullness.
16. A method comprising:
storing a count having a value of greater than one at a reprogrammable storage location;
determining a mode of operation of a processor;
responsive to determining the processor is in a first mode of operation performing (a)-(f):
(a) determining that an event has occurred in response to determining that a number of instruction cycles equal to the count have been executed by the data processor or in response to determining that a number of instructions equal to the count have been processed by the data processor;
(b) in response to determining the event has occurred, storing information at a trace buffer of the integrated circuit, the information related to instruction processing of an active instruction by the data processor;
(c) determining if the trace buffer has obtained a defined level of fullness;
(d) repeating (a) and (b) until the trace buffer obtains a defined level of fullness;
(e) in response to the trace buffer obtaining the defined level of fullness, halting operation of the data processor to prevent a next instruction from being executed; and
(f) in response to receiving an indicator to resume instruction execution, resuming instruction execution at the next instruction and repeating (a)-(f);
responsive to determining the processor is in the first mode of operation performing (g)-(i):
(g) determining that an event has occurred in response to determining that the number of instruction cycles equal to the count have been executed by the data processor or in response to determining that the number of instructions equal to the count have been processed;
(h) in response to determining the event has occurred, storing information at a trace buffer of the integrated circuit, the information related to instruction processing of an active instruction by the data processor;
(i) continuing instruction execution at the next instruction and repeating (g)-(i), wherein information stored at the trace buffer includes overwriting stored information when the trace buffer is full.
17. The method of claim 16 further comprising:
when in the first mode of operation, setting a status bit at a register of the data processor in response to the trace buffer obtaining a defined level of fullness, and
when in the second mode of operation, not setting the status bit in response to the trace buffer obtaining a defined level of fullness.