Granted Patent B2

US 8,332,641 · App. 12/363,259 · Granted Dec 11, 2012

Assignee: Freescale Semiconductor, Inc.

Abstract

Claims (69)

1. A method comprising:

conducting a challenge/response process using a first key value stored in an integrated circuit (IC) device and a challenge value generated at the IC device;

temporarily enabling configuration of the IC device to permanently enable open access to a debug interface of the IC device responsive to confirmation of authentication from the challenge/response process;

temporarily enabling access to the debug interface responsive to confirmation of authentication from the challenge/response process;

performing software evaluation of the IC device while access to the debug interface is temporarily enabled; and

configuring the IC device to permanently enable open access to the debug interface responsive to a failure to identify a defect in the IC device from the software evaluation.

2. The method of claim 1 , further comprising:

performing hardware evaluation of the IC device via the debug interface subsequent to configuring the IC device to permanently enable open access to the debug interface.

3. The method of claim 1 , wherein:

the IC device comprises a default configuration component representative of a default configuration and a customer fuse bank representative of a customer configuration; and

configuring the IC device to permanently enable open access to the debug interface further comprises configuring the IC device to operate using the default configuration represented by the default configuration component in place of the customer configuration represented by the customer fuse bank.

4. The method of claim 3 , further comprising:

receiving, at the IC device, an input directing the IC device to operate using the customer configuration represented by the customer fuse bank; and

configuring the IC device to operate using the customer configuration responsive to receiving the input.

5. The method of claim 1 , wherein:

the IC device is configured to permanently enable open access to the debug interface by placing a fuse in a blown state; and

temporarily enabling configuration of the IC device to permanently enable open access to the debug interface comprises enabling access to the fuse responsive to confirmation of authentication from the challenge/response process.

6. The method of claim 5 , further comprising:

configuring the IC device to permanently enable open access to the debug interface by blowing the fuse while access to the fuse is enabled.

7. The method of claim 1 , wherein conducting the challenge/response process comprises:

generating the challenge value at the IC device;

providing the challenge value to an external device via the debug interface of the IC device;

receiving a response value from the external device via the debug interface; and

confirming authentication using the challenge value and the first key value.

8. The method of claim 7 , further comprising:

signing, at the external device, the challenge value using a second key value to generate the response value, wherein the first key value comprises a public key of a public key infrastructure (PKI) key pair and the second key value comprises a private key of the PKI key pair.

9. The method of claim 1 , further comprising:

receiving, via the debug interface, a signed command file from an external device, the first key value accompanying the signed command file;

storing the first key value at the IC device responsive to confirming authentication of the signed command file using a root key value of the IC device;

conducting a challenge/response process using the first key value stored in the IC device and a challenge value generated at the IC device; and

wherein temporarily enabling configuration of the IC device to permanently enable open access to a debug interface of the IC device responsive to confirmation of authentication from the challenge/response process.

10. A method comprising:

under direction of a first party:

temporarily enabling access to a debug interface of an integrated circuit (IC) device via authentication of the first party by a challenge/response process using a first key of the IC device and a challenge value generated at the IC device;

conducting a software evaluation of the IC device via the debug interface;

permanently enabling open access to the debug interface while authenticated in response to failing to identify an issue with the IC device from the software evaluation; and

providing the IC device to a second party.

11. The method of claim 10 , further comprising:

under direction of the second party:

conducting a hardware evaluation of the IC device via the debug interface.

12. The method of claim 11 , wherein permanently enabling open access to the debug interface of the IC device comprises configuring the IC device to operate using a first configuration represented by a default configuration component in place of a second configuration represented by a fuse bank configured by the first party, and the method further comprising:

under the direction of the second party:

returning the IC device to the first party in response to failing to detect an issue with the IC device via the hardware evaluation; and

under the direction of the first party:

providing a signal to the IC device to direct the IC device to operate using the second configuration represented by the fuse bank; and

configuring the IC device to operate using the second configuration in response to the signal.

13. An integrated circuit (IC) device comprising:

a storage component to store a key value;

a debug interface;

a first fuse operable to control access to the debug interface;

an authenticated debug controller configured to:

conduct a challenge/response process using the key value and a challenge value; and

temporarily enable configuration of the IC device to permanently enable open access to the debug interface by temporarily enabling access to the first fuse in response to confirmation of authentication from the challenge/response process;

a default configuration component representing a first configuration state;

a fuse bank representing a second configuration state; and

wherein the IC device is configured to:

operate using a first configuration state represented by a default configuration component responsive to the first fuse having a non-blown state; and

operate using a second configuration state represented by the fuse bank responsive to the first fuse having a blown state; and

wherein the authenticated debug controller is to configure the IC device to operate using the first configuration state in place of the second configuration state responsive to receipt of a signal at a pin of the IC device.

14. The IC device of claim 13 , wherein the authenticated debug controller is configured to conduct the challenge/response process by:

providing the challenge value to an external device via the debug interface;

receiving a response value from the external device via the debug interface; and

confirming authorization using the challenge value and the response value.

15. The IC device of claim 14 , wherein the authenticated debug controller further is configured to set an access level of the IC device based on an access level associated with the key value and responsive to confirmation of authentication.

16. The IC device of claim 13 , further comprising:

a second fuse; and

wherein the authenticated debug controller is further configured to:

conduct the challenge/response process responsive to the second fuse having a first state; and

enable open access to the debug interface without conducting the challenge/response process responsive to the second fuse having a second state.

Assignments (26)

Continuity (1)