Electrically programmable device with embedded EEPROM and method for making thereof
View Patent ↗A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region.
1. A semiconductor device with an embedded EEPROM device, the semiconductor device comprising:
a one-time programmable device on a silicon wafer; and
an electrically erasable programmable device on the silicon wafer, wherein the one-time programmable device includes:
a first gate oxide layer and a second gate oxide layer, the second gate oxide layer being thinner than the first gate oxide layer;
a first gate on the first gate oxide layer;
a first dielectric layer on the first gate;
an inter-gate oxide layer on the first gate, the inter-gate oxide adapted to shape the first gate for programming the one-time programmable device; and
a second gate on the first dielectric layer, the inter-gate oxide layer, and the second gate oxide layer;
wherein the electrically erasable programmable device includes a tunnel oxide.
2. The device of claim 1 wherein the first dielectric layer comprises a first silicon oxide sub-layer, a silicon nitride sub-layer, and a second silicon oxide sub-layer.
3. The device of claim 1 wherein the inter-gate oxide layer is associated with a thickness ranging from 150 Å to 250 Å.
4. The semiconductor device of claim 1 , wherein the first gate comprises a sharp corner adjacent the inter-gate oxide layer.
5. The semiconductor device of claim 1 , wherein the first gate comprises a sharp corner adjacent the inter-gate oxide layer.
6. The semiconductor device of claim 1 , wherein the third gate is a floating gate.
7. A semiconductor device, comprising:
a substrate including a first device region and a second device region;
a first gate oxide layer in the first device region and the second device region;
a first gate in the first device region;
a second gate and a third gate in the second device region;
a first dielectric layer, a first portion of the first dielectric layer being disposed over the first gate, a second portion of the first dielectric layer being disposed adjacent a sidewall of the first gate, and a third portion of the first dielectric layer being disposed over the third gate;
an inter-gate oxide layer on the first gate and being disposed between the first portion and the second portion of the first dielectric layer;
a second gate oxide layer in the first device region, the second gate oxide layer being on a portion of the substrate not covered by the first gate;
a fourth gate overlying the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region; and
a fifth gate overlying the third portion of the first dielectric layer which is disposed over the third gate in the second device region.
8. The semiconductor device of claim 7 , wherein the first gate comprises a sharp corner adjacent the inter-gate oxide layer.
9. The semiconductor device of claim 7 , wherein first dielectric layer comprises an oxide-nitride-oxide layer.
10. The semiconductor device of claim 7 , wherein the inter-gate oxide layer comprises thermal oxide.
11. The semiconductor device of claim 7 , comprising a one-time programmable device that includes the first gate and the second gate.
12. The semiconductor device of claim 7 , further comprising a tunnel oxide between the third gate and the substrate.
13. The semiconductor device of claim 7 , wherein the third gate is a floating gate.
14. The semiconductor device of claim 7 , wherein a first portion of the first gate oxide layer is disposed between the first gate and the substrate in the first device region.
15. The semiconductor device of claim 7 , wherein a third portion of the first gate oxide layer is disposed between the third gate and the substrate in the second device region.
16. The semiconductor device of claim 7 , wherein a second portion of the first gate oxide layer is disposed between the second gate and the substrate in the second device region.
17. The semiconductor device of claim 7 , comprising an electrically erasable programmable device that includes the second gate, the third gate, and the fifth gate.