Method of stacking flip-chip on wire-bonded chip
Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed.
1. A method of fabricating a semiconductor package, the method comprising:
mounting a first chip onto a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip;
bonding a wire from a first bump pad of the plurality of bump pads to the substrate;
forming an intermediate layer on at least a portion of the active surface of the first chip;
forming a via in the intermediate layer, wherein the via extends to a second bump pad of the plurality of bump pads;
placing a second chip on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer;
forming a corresponding bump on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, wherein the corresponding bump is formed on the second bump pad located on the active surface of the first chip, and wherein a height of the corresponding bump is greater than a height of the intermediate layer; and
heating the corresponding bump formed on the one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip to melt the corresponding bump within the via and thereby form an electrical connection between the second bump pad and the third bump pad.
2. The method of claim 1 , wherein the bump is formed on the second bump pad prior to the first chip being mounted to the substrate.
3. The method of claim 2 , wherein the forming the intermediate layer comprises covering the first bump pad with the intermediate layer.
4. The method of claim 1 , wherein the forming the via comprises forming the via in the intermediate layer correspondingly extending to the corresponding bump.
5. The method of claim 1 , wherein the forming the corresponding bump comprises forming the corresponding bump on the third bump pad on the active surface of the second chip.
6. The method of claim 5 , wherein heating the corresponding bump comprises coupling the corresponding bump to the second bump pad on the active surface of the first chip.
7. The method of claim 6 , wherein the coupling the corresponding second bump to the second bump pad comprises reflowing the corresponding bump.
8. The method of claim 1 , wherein the intermediate layer comprises a paste, a glue, or an adhesive.
9. The method of claim 1 , wherein the intermediate layer comprises silicon, glass, or an organic substrate.
10. The method of claim 1 , wherein the forming the via is performed before forming the intermediate layer on the at least a portion of the active surface.
11. The method of claim 1 , wherein the forming the via comprises laser-etching the via in the intermediate layer.
12. A semiconductor package comprising:
a substrate;
a first chip mounted on the substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip;
a wire bonding a first bump pad of the plurality of bump pads to the substrate;
an intermediate layer disposed on at least a portion of the active surface of the first chip;
a via in the intermediate layer, wherein the via extends to a second bump pad of the plurality of bump pads;
a second chip disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer;
a corresponding bump on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad, wherein the corresponding bump is located on the second bump pad located on the active surface of the first chip, and wherein a height of the corresponding bump is greater than a height of the intermediate layer.
13. The semiconductor package of claim 12 , wherein the substrate is a leadframe.
14. The semiconductor package of claim 12 , wherein the intermediate layer covers the first bump pad.
15. The semiconductor package of claim 12 , wherein the intermediate layer comprises a paste, a glue, or an adhesive.
16. The semiconductor package of claim 12 , wherein the intermediate layer comprises silicon, glass, or an organic substrate.