Error correction and recovery in chained memory architectures
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.
1. A memory unit comprising: a memory section; and an interface section coupled to the memory section, the interface section configured to couple into a chain exterior to the memory unit and configured to accept requests for information from the memory unit, operatively from different directions of information flow in the chain exterior to the memory unit and to respond to the requests; wherein the interface section is configured to allow access to the memory section in response to a request received from either of two directions in the chain to access the memory section.
2. The memory unit of claim 1 , wherein the interface section includes two access channels in each of two different directions to handle requests and two other access channels in each of the two different directions to handle responses.
3. The memory unit of claim 1 , wherein the interface section includes an access channel in each of two different directions to handle requests, another access channel in each of the two different directions to handle responses, and logic to process requests and responses in the two different directions.
4. The memory unit of claim 1 , wherein the interface section includes multiple ports arranged to support multiple chained paths.
5. The memory unit of claim 1 , wherein the interface section includes two access channels and logic configured for bidirectional information flow in a simplex connection.
6. The memory unit of claim 1 , wherein the interface section includes logic configured to determine a path error in information flow when the memory unit is coupled in the chain.
7. The memory unit of claim 6 , wherein the logic includes a counter set to expect a reply within a set time in response to sending information out from the memory unit.
8. The memory unit of claim 6 , wherein the logic includes a retry counter configured to count a number, N>0, of retransmissions of information such that N is a limit to the number of retransmissions in response to determinations that previous corresponding transmissions of the information were in error.
9. The memory unit of claim 8 , wherein the determinations include determination of a bad cyclic redundancy check.
10. The memory unit of claim 1 , wherein the memory unit includes logic to reconfigure the memory unit from being an inner memory unit within the chain to being an end memory unit of the chain in response to a command from a controller or automatically as a result of a path error.