ESD networks for solder bump integrated circuits
Semiconductor dice ( 100, 200 ) of integrated circuit chips are provided with solder bump pads ( 130, 230 ) distributed over active areas of the dice to supply the I/O interconnects without including peripheral wire bond pads. The dice are further provided with protective ESD structures ( 140 p/ 140 i , 240 p/ 240 i ) arranged in a network that includes ESD structures that extend into the interior areas of the dice. This allows the ESD structures to be placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.
1. An integrated circuit chip including a semiconductor die having an interior area bounded by a peripheral area, the semiconductor die comprising:
at least one functional domain located in the die interior area;
I/O circuitry providing I/O interconnects for the at least one functional domain, the I/O circuitry including a plurality of solder bump pads without including peripheral wire bond pads, at least a portion of the bump pads being interior bump pads distributed over the die interior area; and
an ESD network to protect components of the die from electrostatic discharge, the ESD network including a plurality of ESD structures located in the die interior area, each of the ESD structures placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between the interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.
2. The integrated circuit chip of claim 1 , wherein the at least one functional domain includes an RF macro.
3. The integrated circuit chip of claim 1 , wherein the at least one functional domain includes a digital macro.
4. The integrated circuit chip of claim 1 , wherein the ESD network further includes an ESD ring positioned near the die periphery and interior ESD structures positioned in the die interior area.
5. The integrated circuit chip of claim 1 , wherein the I/O interconnects are routed to the ESD through a metal redistribution layer of the die.
6. The integrated circuit chip of claim 1 , wherein the I/O circuitry provides solder bump pad I/O interconnects for the entire die without including peripheral wire bond pads.
7. The integrated circuit chip of claim 1 , wherein the integrated circuit chip is implemented as a SoC.
8. The integrated circuit chip of claim 1 , wherein the integrated circuit chip is implemented as a radio-baseband SoC.
9. The integrated circuit chip of claim 1 , wherein the average interconnect length between the interior bump pads and the ESD structures is no more than three times the average spacing between bump pads.
10. The integrated circuit chip of claim 1 , wherein the average interconnect length between the interior bump pads and the ESD structures is no more than two times the average spacing between bump pads.
11. The integrated circuit chip of claim 1 , wherein the average interconnect length between the interior bump pads and the ESD structures is in a range of about 50 microns to 150 microns.
12. The integrated circuit chip of claim 1 , wherein the interior bump pads distributed over the die interior area are electrically connected via leads to the plurality of ESD structures located in the die interior area.
13. The integrated circuit chip of claim 12 , wherein the interior bump pads are electrically connected via leads to a respective one of the interior ESD structures to reduce an average interconnect length between the interior bump pads and the ESD network.
14. A method for designing an integrated circuit chip including a semiconductor die having an interior area bounded by a peripheral area and at least one functional domain located in the die interior area, the method comprising:
distributing solder bump pads over a surface of the die to provide I/O interconnects for the at least one functional domain without including peripheral wire bond pads, at least a portion of the bump pads being interior bump pads distributed over the die interior area; and
providing an ESD network of ESD structures to protect components of the die from electrostatic discharge, at least a portion of the ESD structures located in the die interior area, each of the ESD structures being placed proximate to respective power and ground connections and being positioned to reduce an average interconnect length between the interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.
15. An integrated circuit chip including a semiconductor die having an interior area bounded by a peripheral area, the semiconductor die comprising:
at least one functional domain of circuitry located in the die interior area;
I/O circuitry providing I/O interconnects for the at least one functional domain, the I/O circuitry including a plurality of solder bump pads without including peripheral wire bond pads, at least a portion of the bump pads being interior bump pads distributed over the die interior area; and
an ESD network to protect components of the die from electrostatic discharge, the ESD network including an ESD ring arranged around the die periphery and interior ESD structures extending from the ESD ring into the die interior area for providing ESD protection thereto, the ESD ring and the ESD structures being positioned and configured to reduce an average interconnect length between the interior bump pads and the ESD network relative to an average path length between the interior bump pads and the die peripheral area.