IP Library › Granted Patent US 8,441,113
Granted Patent B2
US 8,441,113 · App. 13/407,003 · Granted May 14, 2013

Elimination of RDL using tape base flip chip on flex for die stacking

Inventor: Teck Kheng Lee (Singapore, SG)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,441,113
App. No.
13/407,003
Granted
May 14, 2013
Kind
B2
Abstract

A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies that incorporate the flexible film interposer, and methods of fabricating the devices and assemblies are provided. The incorporation of the flexible film interposer achieves densely packaged semiconductor devices, without the need for a redistribution layer (RDL).

Claims (38)

1. A die assembly, comprising:

an interposer comprising a substrate having a first surface and a second surface, a recess and a slot extending through the substrate from the first surface to the second surface, and a trace on the second surface extending across the slot and the recess;

a first die comprising a conductive bump situated on the first surface of the substrate with the bump situated in the recess in contact with the trace, and the slot exposed on the first surface of the substrate; and

a second die comprising a bond pad situated on the second surface of the substrate with the bond pad aligned with the slot and in contact with at least a portion of the trace extending across the slot.

2. A die assembly, comprising a first die on an interposer, the interposer comprising a first surface and a second surface, a recess and a slot extending therethrough from the first surface to the second surface, and a trace on the second surface extending across the slot and the recess, a conductive bump of the first die situated within the recess of the interposer in contact with the trace, and the slot exposed at the first surface of the interposer, and a second die on the second surface of the interposer, wherein a bond pad, the trace, and the slot are aligned and the bond pad is in contact with the trace.

3. A die assembly, comprising:

an interposer having a recess and a slot extending therethrough from a first surface to a second surface, and a trace on the second surface extending across the slot and the recess;

a first die situated on the first surface of the interposer with a conductive bump of the first die situated within the recess of the interposer in contact with the trace; and

a second die on the second surface of the interposer with a bond pad of the second die in contact with at least a portion of the trace extending across the slot and aligned with the slot, wherein the trace is accessible within the slot from the first surface of the interposer.

4. A die assembly, comprising:

first and second dies in a vertically stacked arrangement with an interposer situated therebetween;

the first die situated on a first surface of the interposer with a conductive bump of the first die situated within a recess extending through the interposer and in contact with a trace on a second surface of the interposer; and

the second die situated on the second surface of the interposer with a bond pad of the second die in contact with the trace, wherein the bond pad, the trace, and the slot are aligned and

the trace accessible within the slot from the first surface of the interposer.

5. The die assembly of claim 4 , further comprising an encapsulation material within the recess over the conductive bump.

6. The die assembly of claim 4 , wherein the second die is mounted on a substrate.

7. The die assembly of claim 6 , wherein the substrate comprises a non-flexible material.

8. The dies assembly of claim 7 , wherein the substrate comprises a material selected from the group consisting of bismaleimide triazine (BT), fiberglass laminate, FR5 laminate and ceramic.

9. A die assembly, comprising:

first and second dies in a vertically stacked arrangement with an interposer situated therebetween;

the first die situated on a first surface of the interposer with a conductive bump of the first die situated within a recess extending through the interposer and in contact with a trace on a second surface of the interposer;

a first side of the second die situated on the second surface of the interposer with a bond pad of the second die in contact with the trace and aligned with a slot extending through the interposer; and

a substrate mounted on a second side of the second die with a terminal pad on the substrate connected to the trace within the slot.

10. The die assembly of claim 9 , wherein the trace is wire bonded to the terminal pad.

11. The die assembly of claim 9 , wherein the trace is connected to the terminal pad by a TAB bond.

12. The die assembly of claim 9 , wherein the substrate comprises contacts for coupling the die assembly to external circuitry.

13. The die assembly of claim 9 , wherein the substrate comprises contacts for coupling the die assembly to a device selected from the group consisting of a motherboard, a program logic controller and a testing apparatus.

14. The die assembly of claim 9 , wherein at least a portion of the die assembly is encapsulated.

15. A method of fabricating a stacked die assembly, comprising:

mounting a first die on a first surface of an interposer such that a conductive bump on a surface of the first die is situated within a recess extending through the interposer from the first surface to a second surface, a slot extending through the interposer is exposed adjacent to the first die, and a trace on the second surface of the interposer extends across the recess and is in contact with the conductive bump of the first die and extends across the slot and is accessible within the slot from the first surface of the interposer.

16. The method of claim 15 , further comprising mounting a second die on the second surface of the interposer opposite the first die in a vertically stacked arrangement with a bond pad of the second die aligned with the slot and in contact with the trace.

17. A method of fabricating a stacked die assembly, comprising:

mounting first and second dies in a vertically stacked arrangement with an interposer situated therebetween;

wherein the first die is mounted on a first side of the interposer with a conductive bump of the first die situated within a recess in the interposer in contact with a trace on a second side of the interposer; and

wherein the second die is mounted on the second side of the interposer with a bond pad of the second die in contact with the trace and aligned through the interposer with a slot and accessible within the slot from the first side of the interposer.

18. A method of fabricating a stacked die assembly, comprising:

flip chip mounting a first die on a first side of an interposer, a conductive bump of the first die situated within a recess in the interposer in contact with a trace on a second side of the interposer; and

mounting a second die on the second side of the interposer in a stacked arrangement with the first die, a bond pad of the second die in contact with the trace and accessible within the slot from the first side of the interposer, and the bond pad, the trace, and the slot are aligned through the interposer.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Priority Claims (1)
SG 200200130-3 · Jan 9, 2002 · national
Continuity (4)
Continuation 11714072 · Mar 5, 2007
Continuation 10853377 · May 25, 2004
Division 10050507 · Jan 16, 2002
Related Publication 20120153468A1 · Jun 21, 2012