Memory devices and methods of operating memory
View Patent ↗Methods and apparatus for synchronizing a delay locked loop, such as delay locked loops used with NAND memories are disclosed. In at least one embodiment, one or both of a clock and the delay locked loop are stopped for energy savings. A synchronization start signal can be provided by the NAND memory or a controller to start the clock and/or delay locked loop, and to synchronize the delay locked loop to the clock before competing the read operation.
1. A method, comprising:
monitoring a read operation in a memory; and
synchronizing a delay locked loop of the memory to a clock with a ready/busy signal activated approximately a synchronization time before an expected completion of the read operation.
2. The method of claim 1 , wherein monitoring comprises:
monitoring a status indicator responsive to a read status command.
3. The method of claim 2 , wherein the status indicator is a status bit in a status register.
4. The method of claim 2 , wherein synchronizing comprises:
starting the clock responsive to the status indicator; and
starting the delay locked loop responsive to the status indicator.
5. The method of claim 2 , wherein the status indicator comprises a synchronization start signal.
6. The method of claim 2 , wherein the status indicator comprises a flag.
7. The method of claim 2 , wherein synchronizing comprises starting the delay locked loop responsive to the status indicator.
8. The method of claim 1 , and comprising:
stopping the clock and the delay locked loop after the read operation is complete.
9. The method of claim 8 , wherein synchronization further comprises:
starting the clock and the delay locked loop when synchronization for a next read operation begins.
10. The method of claim 1 , wherein monitoring comprises:
providing to a controller a read time parameter of the memory.
11. The method of claim 10 , wherein synchronizing comprises starting the clock at a particular time during the read operation based on the read time parameter.
12. The method of claim 1 , wherein synchronization comprises synchronizing the delay locked loop to the clock with the ready/busy signal beginning at approximately a maximum synchronization time before the read operation is complete.
13. The method of claim 1 , wherein synchronization comprises synchronizing the delay locked loop to the clock with the ready/busy signal beginning at approximately a minimum synchronization time before the read operation is complete.
14. The method of claim 1 , wherein synchronization comprises synchronizing the delay locked loop to the clock with the ready/busy signal beginning at approximately an average synchronization time before the read operation is complete.
15. The method of claim 1 , wherein the synchronization time is based on a frequency of the delay locked loop.
16. The method of claim 1 , wherein synchronization is started when a trigger pulse is presented as the ready/busy signal on a ready/busy pin, the trigger pulse only responsive to a pulse in the synchronization signal having a duration of no more than a trigger time.
17. The method of claim 1 , wherein monitoring the read operation comprises monitoring progress of the read operation and determining when the read operation is nearing completion.
18. The method of claim 1 , wherein synchronizing comprises starting synchronization after starting the read operation and responsive to the ready/busy signal.
19. The method of claim 1 , wherein monitoring comprises monitoring by the memory.
20. The method of claim 1 , wherein monitoring comprises monitoring by a controller.
21. A method, comprising:
monitoring a read operation in a memory; and
synchronizing a delay locked loop of the memory to a clock before completing the read operation, wherein synchronizing comprises:
synchronizing the delay locked loop with the clock responsive to a pulse of a ready/busy signal, the pulse of a duration less than a trigger time.
22. A method, comprising:
monitoring a read operation in a memory; and
synchronizing a delay locked loop of the memory to a clock before completing the read operation, wherein monitoring comprises monitoring a read time of the read operation using an average array read time per memory page and per memory page type for the memory; and
wherein synchronizing comprises synchronizing the delay locked loop to the clock beginning at a determined synchronization time before an expected completion of the read operation.
23. The method of claim 22 , wherein synchronizing comprises:
starting the clock and the delay locked loop at a start of synchronizing.
24. A method, comprising:
monitoring a read operation in a memory; and
synchronizing a delay locked loop of the memory to a clock before completing the read operation, wherein the memory is on a first die of a multiple die system sharing a common data bus, and further comprising:
determining when a first die data output operation after its read operation is nearing completion; and
synchronizing a DLL of the second die responsive to a signal to the second die that the data output operation of the first die is nearing completion.
25. The method of claim 24 , wherein the signal to the second die is a signal provided by the first die.
26. The method of claim 25 , wherein the signal provided by the first die is provided using a signal shared by the first and the second dies.
27. The method of claim 24 , wherein the signal to the second die is a signal provided by a controller.
28. The method of claim 27 , wherein the signal provided by the controller is provided by stopping the data output operation of the first die, starting synchronization of the second die DLL, and continuing the data output operation of the first die.
29. The method of claim 27 , wherein the signal provided by the controller is provided using a signal unique to the second die.
30. A method, comprising:
stopping operation of a delay locked loop and a clock in a memory after completion of a read operation;
monitoring a subsequent read operation in the memory;
starting the delay locked loop and the clock upon receipt of a start signal; and
synchronizing the delay locked loop to the clock before completing the read operation.
31. The method of claim 30 , wherein the start signal comprises a status indicator.
32. The method of claim 31 , wherein the status indicator is a status bit in a status register.
33. A method, comprising:
stopping operation of a delay locked loop and a clock in a memory after completion of a read operation;
monitoring a subsequent read operation in the memory;
starting the delay locked loop and the clock upon receipt of a start signal; and
synchronizing the delay locked loop to the clock before completing the read operation, wherein the start signal comprises a command from a controller to start synchronization at a time before the read operation completion, the time determined using an average array read time per memory page and per memory page type for the memory.
34. A method, comprising:
stopping operation of a delay locked loop and a clock in a memory after completion of a read operation;
monitoring a subsequent read operation in the memory;
starting the delay locked loop and the clock upon receipt of a start signal; and
synchronizing the delay locked loop to the clock before completing the read operation, wherein the start signal comprises a trigger pulse presented on a ready/busy pin, the trigger pulse having a duration of no more than a determined trigger time.
35. A method, comprising:
stopping operation of a delay locked loop and a clock in a memory after completion of a read operation;
monitoring a subsequent read operation in the memory;
starting the delay locked loop and the clock upon receipt of a start signal; and
synchronizing the delay locked loop to the clock before completing the read operation, wherein the memory is on a first die of a multiple die system sharing a common data bus, and further comprising:
determining when a first die data output operation after its read operation is nearing completion; and
synchronizing a DLL of the second die responsive to a signal to the second die that the data output operation of the first die is nearing completion.
36. A memory device, comprising:
an array of memory cells;
a delay locked loop for synchronization to a clock; and
circuitry for control and/or access of the array of memory cells, the control circuitry configured to perform a method comprising:
monitoring a read operation in a memory; and
synchronizing the delay locked loop of the memory to the clock with a ready/busy signal activated approximately a synchronization time before an expected completion of the read operation.
37. A memory device, comprising:
an array of memory cells;
a delay locked loop for synchronization to a clock; and
circuitry for control and/or access of the array of memory cells, the control circuitry configured to perform a method comprising:
monitoring a read operation in a memory; and
synchronizing the delay locked loop of the memory to the clock before completing the read operation, wherein the array of memory cells is on a first die of a multiple die system sharing a common data bus, and wherein the circuitry is further configured to:
determine when a first die data output operation after its read operation is nearing completion; and
synchronize a DLL of the second die responsive to a signal to the second die that the data output operation of the first die is nearing completion.