Method and apparatus for protection against process-induced charging
A semiconductor device ( 400 ) for improved charge dissipation protection includes a substrate ( 426 ), a layer of semiconductive or conductive material ( 406 ), one or more thin film devices ( 408 ) and a charge passage device ( 414 ). The thin film devices ( 408 ) are connected to the semiconductive or conductive layer ( 406 ) and the charge passage device ( 414 ) is coupled to the thin film devices ( 408 ) and to the substrate ( 426 ) and provides a connection from the thin film devices ( 408 ) to the substrate ( 426 ) to dissipate charge from the semiconductive/conductive layer ( 406 ) to the substrate ( 426 ).
1. A semiconductor device comprising:
a semiconductor substrate;
an at least semiconductive layer, wherein the at least semiconductive layer is either a semiconductive layer or a conductive layer;
one or more thin film devices that comprise gate electrodes connected to the at least semiconductive layer for dissipating charge therefrom wherein the one or more thin film devices are coupled to a common node; and
a single charge passage device coupled to the one or more thin film devices at a single node and to the substrate for providing a connection from the one or more thin film devices to the substrate to dissipate charge from the at least semiconductive layer to the substrate wherein an electronic charge leakage device that electrically isolates portions of the at least semiconductive layer is coupled between the single charge passage device and the substrate wherein the single charge passage device comprises a gate oxide capacitor.
2. The semiconductor device of claim 1 wherein the semiconductor device comprises a memory device including one or more core memory arrays, each of the one or more core memory arrays having a plurality of word lines, and wherein the at least semiconductive layer includes the plurality of word lines.
3. The semiconductor device of claim 2 wherein the one or more thin film devices includes a plurality of thin film devices coupled to each of the one or more core memory arrays, and wherein each of the plurality of word lines is connected to one of the plurality of thin film devices.
4. The semiconductor device of claim 2 wherein the memory device includes a plurality of core memory arrays.
5. The semiconductor device of claim 4 wherein the one or more thin film devices includes a plurality of thin film devices coupled to each of the plurality of core memory arrays, and wherein each of the plurality of word lines is connected to one of the plurality of thin film devices.
6. The semiconductor device of claim 5 further comprising a spine coupled to the one or more core memory arrays and connected to each of the plurality of thin film devices, the spine also connected to the charge passage device to provide the connection from the plurality of thin film devices to the substrate to dissipate charge from the plurality of word lines to the substrate.
7. The semiconductor device of claim 6 further comprising one or more additional charge passage devices, each of the charge passage device and the one or more additional charge passage devices connected to the spine to provide multiple connections from the plurality of thin film devices to the substrate to dissipate charge from the plurality of word lines to the substrate.
8. The semiconductor device of claim 1 wherein the substrate includes a doped well formed therein and wherein the charge passage device couples the one or more thin film devices to the doped well.
9. The semiconductor device of claim 1 wherein the one or more thin film devices are integrally formed in the at least semiconductive layer.
10. The semiconductor device of claim 9 wherein the one or more thin film devices transport charge from a first portion of the at least semiconductive layer to a second portion of the at least semiconductive layer, the second portion of the at least semiconductive layer connected to the charge passage device.
11. The semiconductor device of claim 10 wherein the first portion of the at least semiconductive layer comprises a gate of one or more transistors.
12. The semiconductor device of claim 1 wherein the at least semiconductive layer includes a gate of one or more transistors.
13. The semiconductor device of claim 1 wherein the at least semiconductive layer is a polysilicon layer.