Planar and nanowire field effect transistors
A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.
1. A method for forming an integrated circuit, the method comprising:
forming a first nanowire suspended above an insulator substrate, wherein the first nanowire is attached to a first silicon on insulator (SOI) pad region and a second SOI pad region which regions are disposed on the insulator substrate, wherein a second nanowire is disposed on the insulator substrate and is attached to a third SOI pad region and a fourth SOI pad region which regions are disposed on the insulator substrate, and an SOI slab region that is disposed on the insulator substrate; and
forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.
2. The method of claim 1 , wherein the first nanowire, the second nanowire, the SOI pad regions, and the SOI slab region are formed simultaneously.
3. The method of claim 1 , wherein the first gate, the second gate, and the third gate are formed simultaneously.
4. The method of claim 1 , wherein the method further comprises simultaneously forming:
a source region on a first side of the first gate;
a source region on a first side of the second gate;
a source region on a first side of the third gate;
a drain region on a second side of the first gate;
a drain region on a second side of the second gate; and
a drain region on a second side of the third gate.
5. The method of claim 1 , wherein the method further comprises smoothing the first nanowire and the second nanowire prior to forming the first gate and the second gate.
6. The method of claim 1 , wherein the method further comprises:
forming spacers on each side of the first gate, the second gate, and the third gate; and
epitaxially thickening exposed portions of the first nanowire, the second nanowire, and the SOI slab region following the formation of the first gate, the second gate, and the third gate.
7. A method for forming an integrated circuit, the method comprising:
forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate; and
forming a first gate surrounding a portion of the first nanowire and a second gate on a portion of the second nanowire.
8. The method of claim 7 , wherein the first nanowire, the second nanowire, and the SOI pad regions are formed simultaneously.
9. The method of claim 7 , wherein the first gate and the second gate are formed simultaneously.
10. The method of claim 7 , wherein the method further comprises simultaneously forming:
a source region on a first side of the first gate;
a source region on a first side of the second gate;
a drain region on a second side of the first gate; and
a drain region on a second side of the second gate.
11. The method of claim 7 , wherein the method further comprises smoothing the first nanowire and the second nanowire prior to forming the first gate and the second gate.
12. The method of claim 7 , wherein the method further comprises:
forming spacers on each side of the first gate and the second gate; and
epitaxially thickening exposed portions of the first nanowire and the second nanowire following the formation of the first gate and the second gate.
13. A method for forming an integrated circuit, the method comprising:
forming a nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region, the first SOI pad region and the second SOI pad region are disposed on an insulator substrate, and a SOI slab region that is disposed on the insulator substrate; and
forming a first gate on a portion of the first nanowire and a second gate on a portion of the SOI slab region.
14. The method of claim 13 , wherein the first nanowire is suspended above the insulator substrate by the first SOI pad region and the second SOI pad region.
15. The method of claim 13 , wherein the first nanowire is disposed on the insulator substrate.
16. The method of claim 13 , wherein the first nanowire, the SOI pad regions, and the SOI slab region are formed simultaneously.
17. The method of claim 13 , wherein the first gate and the second gate are formed simultaneously.
18. The method of claim 13 , wherein the method further comprises simultaneously forming:
a source region on a first side of the first gate;
a source region on a first side of the second gate;
a drain region on a second side of the first gate; and
a drain region on a second side of the second gate.
19. The method of claim 13 , wherein the method further comprises smoothing the first nanowire prior to forming the first gate and the second gate.
20. The method of claim 13 , wherein the method further comprises:
forming spacers on each side of the first gate and the second gate; and
epitaxially thickening exposed portions of the first nanowire and the SOI slab region following the formation of the first gate and the second gate.