IP Library Granted Patent US 8,455,995
Granted Patent B2
US 8,455,995 · App. 12/762,085 · Granted Jun 4, 2013

TSVs with different sizes in interposers for bonding dies

Inventors: Po-Hao Tsai (Zhongli, TW); Jing-Cheng Lin (Hsin-Chu, TW); Chen-Hua Yu (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,455,995
App. No.
12/762,085
Granted
Jun 4, 2013
Kind
B2
Abstract

A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

Claims (36)

1. A device comprising:

an interposer comprising a substrate having a top surface and a bottom surface, wherein the interposer is substantially free from integrated circuit devices formed therein;

a plurality of through-substrate vias (TSVs) penetrating through the substrate, wherein the plurality of TSVs comprises a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension; and

a first interconnect structure formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

2. The device of claim 1 , wherein the first horizontal dimension is greater than the second horizontal dimension of the second TSV.

3. The device of claim 2 , wherein a ratio of the first horizontal dimension to the second horizontal dimension is greater than about 1.5.

4. The device of claim 1 , wherein the first length is greater than the second length.

5. The device of claim 1 further comprising:

a first die overlying the first interconnect structure; and

a second die underlying the bottom surface of the substrate and electrically coupled to the second TSV.

6. The device of claim 5 , wherein the second die is bonded to the second TSV.

7. The device of claim 5 further comprising a molding compound underlying the bottom surface of the substrate, wherein the first TSV extends to penetrate the molding compound.

8. The device of claim 7 , wherein the second die is formed in the molding compound.

9. The device of claim 8 further comprising a metal bump on a bottom surface of the molding compound and electrically coupled to the first TSV.

10. The device of claim 7 further comprising a second interconnect structure underlying the molding compound and electrically connected to the first TSV.

11. The device of claim 10 further comprising a metal bump underlying the second interconnect structure and electrically coupled to the first TSV.

12. The device of claim 5 , wherein the substrate comprises a recess extending from the bottom surface of the substrate into the substrate, and wherein at least a portion of the second die is located in the recess.

13. The device of claim 1 , wherein the substrate comprises a semiconductor substrate, and wherein the interposer is substantially free from active devices therein.

14. The device of claim 13 , wherein the substrate comprises a silicon substrate.

15. A device comprising:

an interposer comprising a substrate having a top surface and a bottom surface;

a plurality of through-substrate vias (TSVs) penetrating through the substrate, wherein the plurality of TSVs comprises a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension;

a molding compound underlying the bottom surface of the substrate, wherein the first TSV extends to penetrate the molding compound;

a first interconnect structure formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs;

a first die overlying the first interconnect structure; and

a second die underlying the bottom surface of the substrate and electrically coupled to the second TSV.

16. The device of claim 15 , wherein the second die is formed in the molding compound.

17. The device of claim 15 further comprising a metal bump on a bottom surface of the molding compound and electrically coupled to the first TSV.

18. The device of claim 15 further comprising a second interconnect structure underlying the molding compound and electrically connected to the first TSV.

19. A device comprising:

a interposer comprising a substrate having a top surface and a bottom surface, wherein the substrate comprises a recess extending from the bottom surface of the substrate into the substrate;

a plurality of through-substrate vias (TSVs) penetrating through the substrate, wherein the plurality of TSVs comprises a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension;

a first interconnect structure formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs;

a first die overlying the first interconnect structure; and

a second die underlying the bottom surface of the substrate and electrically coupled to the second TSV, wherein at least a portion of the second die is located in the recess.

20. The device of claim 19 further comprising a molding compound underlying the bottom surface of the substrate, wherein the first TSV extends to penetrate the molding compound, wherein the second die is disposed in the molding compound.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2010
From: TSAI, PO-HAO; LIN, JING-CHENG; YU, CHEN-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024249/0962 →
Continuity (1)
Related Publication 20110254160A1 · Oct 20, 2011