IP Library › Granted Patent US 8,456,016
Granted Patent B2
US 8,456,016 · App. 12/729,821 · Granted Jun 4, 2013

Method and core materials for semiconductor packaging

Inventors: Yonggang Li (Chandler, AZ); Amruthavalli P. Alur (Chandler, AZ); Devarajan Balaraman (Chandler, AZ); Xiwang Qi (Scottsdale, AZ); Charan K. Gurumurthy (Higley, AZ)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,456,016
App. No.
12/729,821
Granted
Jun 4, 2013
Kind
B2
Abstract

A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.

Claims (22)

1. A semiconductor package, comprising:

a semiconductor substrate that comprises a core, the core comprising one or more materials selected from a group comprising ceramics and glass dielectrics;

a set of one or more inner conductive elements that is provided on the core;

a set of one or more outer conductive elements that is provided on an outer side of the substrate;

a semiconductor die to couple to the substrate via one or more of the outer conductive elements; and

a dielectric layer that is to insulate the inner conductive elements from the outer conductive elements.

2. The package of claim 1 , wherein the ceramics comprise one or more of alumina, zirconia, carbides, nitrides.

3. The package of claim 1 , wherein the ceramics comprise 50% to 100% alumina that is compounded with other ceramic elements.

4. The package of claim 1 , wherein the glass dielectrics comprise one or more from fused silica, quartz, and sapphire.

5. The package of claim 1 , wherein the one or more materials have a Young's modulus that is higher than 100 GPa at a room temperature.

6. The package of claim 1 , wherein the dielectric layer comprises glass fiber reinforced dielectric.

7. The package of claim 1 , further comprising:

a plated through hole to form interconnection to selectively couple at least the conductive elements on the core.

8. A system, comprising:

a semiconductor package;

a semiconductor substrate in the package that comprises a core, the core comprising a material selected from a group comprising ceramics and glass dielectrics;

a semiconductor die to couple to the substrate via a first conductive element on the substrate;

a dielectric layer that is provided on the core, the dielectric layer comprises glass fiber reinforced dielectric.

9. The system of claim 8 , wherein the material has a Young's modulus that is higher than 100 GPa at a room temperature.

10. The system of claim 8 , further comprising:

a plated through hole that is formed in the substrate to couple the first conductive element to a second conductive element on the core.

11. The system of claim 8 , wherein the core comprises one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, and sapphire.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076065/0923 →
Continuity (2)
Division 12242414 · Sep 30, 2008
Related Publication 20100289154A1 · Nov 18, 2010