Method for dual energy implantation for ultra-shallow junction formation of MOS devices
View Patent ↗A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).
1. A method for forming a MOS device comprising:
providing a semiconductor substrate, the semiconductor substrate comprising a surface region;
forming a gate dielectric layer overlying the surface region of the semiconductor substrate;
forming a gate layer overlying the gate dielectric layer;
patterning the gate layer to form a gate structure including a first edge and a second edge, the gate structure having a width of 90 nanometers and less; and
concurrently implanting a first dose of a selected species at a first depth with a first energy and a second dose of the selected species at a second depth with a second energy using the gate structure as a mask to form a lightly doped drain (LDD) region, the first depth being a predetermined first depth from the surface region, the second depth being a predetermined second depth from the surface region;
wherein the first energy is different from the second energy;
wherein the first and second doses are implanted at a same incident angle relative to the surface region of the semiconductor substrate.
2. The method of claim 1 wherein the first depth is shallower than the second depth.
3. The method of claim 1 wherein the gate structure is overlying an effective channel region that has a length of the width of the gate structure.
4. The method of claim 1 wherein the semiconductor substrate is essentially silicon material.
5. The method of claim 1 further comprising:
diffusing the selected species using a thermal treatment process to form a source region and a drain region adjacent to the gate structure; and
etching a portion of the source region and a portion of the drain region.
6. The method of claim 5 further comprising filling the etched portions of source and drain regions with a silicon germanium bearing material.
7. The method of claim 1 wherein the first depth comprises a dopant peak of the selected species at about 10 Angstroms.
8. The method of claim 1 wherein the MOS device is characterized by a saturation current Isat and a leakage current Ioff.
9. The method of claim 1 wherein the second dose is substantially equal to the first dose, and the second energy is about 10 times higher than the first energy.
10. The method of claim 1 wherein the second energy is about 500 eV and the second dose is about 1 E15 atoms/cm2 and the first energy is about 50 eV and the first dose is from about 1 E15 atoms/cm2 to about 3 E15 atoms/cm2.
11. The method of claim 1 wherein the second energy is higher than the first energy.
12. The method of claim 1 wherein the first dose is about 1 to 3 times higher than the second dose.
13. The method of claim 1 wherein the selected species comprises n-type dopants.
14. The method of claim 1 wherein the selected species comprises p-type dopants.
15. The method of claim 1 wherein the selected species is selected from the group consisting of phosphorous (P), arsenic (As), and antimony (Sb).
16. The method of claim 1 wherein the same incident angle is substantially perpendicular to the surface region of the semiconductor substrate.