Single gate inverter nanowire mesh

1. A field-effect transistor (FET) inverter, comprising:

a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant, and wherein the nanowire channels in any given one of the device layers have a pitch of from about 10 nm to about 200 nm, and wherein the device layers are separated from one another in the stack by in-situ doped sacrificial layers which are present in the stack between the source regions and the drain regions of the device layers but not between the nanowire channels in the stack;

a gate common to each of the device layers surrounding the nanowire channels;

a first contact to the source regions of the one or more device layers doped with an n-type dopant;

a second contact to the source regions of the one or more device layers doped with a p-type dopant; and

a third contact common to the drain regions of each of the device layers.

2. The FET inverter of claim 1 , wherein the nanowire channels in any given one of the device layers have a pitch of from about 40 nm to about 50 nm.

3. The FET inverter of claim 1 , wherein the nanowire channels of adjacent device layers in the stack are separated from one another by a gap of from about five nm to about 20 nm based on a thickness of the sacrificial layers between the adjacent device layers in the stack.

4. The FET inverter of claim 1 , wherein the n-type dopant comprises one or more of phosphorous and arsenic.

5. The FET inverter of claim 1 , wherein the p-type dopant comprises boron.

6. The FET inverter of claim 1 , wherein the gate is separated from the nanowire channels by a dielectric.

7. The FET inverter of claim 1 , further comprising spacers between the source and drain regions of the device layers and the gate.

8. The FET inverter of claim 1 , wherein the gate comprises one or more of polysilicon and a metal.

9. The FET inverter of claim 1 , wherein the first contact serves as a ground contact of the inverter, the second contact serves as a power contact of the inverter, the gate serves as an input contact of the inverter and the third contact serves as an output contact of the inverter.

10. The FET inverter of claim 1 , wherein the third contact shorts the drain regions of each of the device layers.

11. The FET inverter of claim 1 , further comprising an electrically insulating layer separating the source and drain regions of the one or more device layers doped with the n-type dopant from the source and drain regions of the one or more device layers doped with the p-type dopant.

12. The FET inverter of claim 11 , wherein the one or more device layers doped with the n-type dopant are located below the electrically insulating layer and the one or more device layers doped with the p-type dopant are located above the electrically insulating layer.

13. The FET inverter of claim 1 , wherein the nanowire channels are undoped.

14. The FET inverter of claim 11 , wherein the electrically insulating layer comprises a crystalline electrically insulating material such that the device layers located in the stack above the electrically insulating layer comprise an epitaxial material.

15. The FET inverter of claim 11 , further comprising:

a recessed portion of the stack and an unrecessed portion of the stack in the source regions of the device layers above the electrically insulating layer, wherein the recessed portion and the unrecessed portion are separated by a spacer, and wherein the first contact is to the recessed portion of the stack and the second contact is to the unrecessed portion of the stack.